Design of multiplexer using AlteraFLEX10K programmable logic device

    Abstract: Taking the design of a three-way fixed time division multiplexer as an example, this article introduces the top-down design method of Altera's FLEX10K embedded programmable logic device, and gives the FLEX 10K embedded programmable device in Mux+plus Ⅱ Simulation implementation of multi-channel time division multiplexer in environment.

    Keywords: Programmable logic device Mux+plus Ⅱ time division multiplexing simulation FLEX 10K

1 Altera FLEX 10K Overview

Altera's FLEX 10K embedded programmable series products are new devices that organically combine traditional programmable logic with embedded gate arrays. Because it has two unique logic application structures - embedded array and logic array, the FLEX 10K series products have revolutionized the programmable structure and become the mainstream of the gate array market.

From 10k to 250k typical gates, the FLEX 10K series has three generations of products, and each generation has higher performance, lower cost and power consumption than the previous generation.

Altera's fast, efficient and easy-to-operate MAX+PLUS II design software can provide support for exchanging FLEX 10K series products. Combining MAX+PLUS II software with a broad range of IP units available for FLEX 10K devices can effectively simplify the design work and greatly shorten the design process. These features will make the FLEX 10K series an advanced and effective gate array replacement today.

2 Performance characteristics of FLEX 10K devices

FLEX 10K series devices are an embedded PLD product. FLEX (Flexible Logic Cell Array) uses reconfigurable CMOS SRAM cells, and its structure integrates all the features required to implement a general-purpose multi-function gate array. The FLEX 10K series of devices has a capacity of up to 250,000 gates, so it can integrate the entire digital system, including 32-bit multi-bus systems, into a single device with high density, high speed and high performance. Features of FLEX 10K devices are as follows:

●Embedded programmable devices can provide integrated system and single programmable logic device performance;

●High density, providing 10,000 to 250,000 available gates and 6144 to 40960 bits of internal RAM;

●Low power consumption: Most devices draw less than 0.5mA in static mode and can operate at 2.5V, 3.3V or 5.0V voltages;

●High speed: clock locking and clock bootstrapping options can be used to reduce clock delay/overshoot and clock multiplication respectively; the device contains tree-shaped distributed low-distortion clocks and has fast settling time and clock-to-output delay external register;

●Flexible interconnection method, using fast channel continuous distribution structure with fast and predictable interconnection delay, which can realize dedicated carry chain for fast addition, counting, comparison and other arithmetic logic functions; and can realize high-speed, multi-input logic Dedicated cascade chain of functions; it can also realize three-state simulation of the internal three-state bus; it has up to six global clock signals and four global clear signals;

●Support multi-voltage I/O interface and comply with PCI2.2 bus standard;

●With multiple configuration methods and multiple packaging forms.

3 Top-down design method

The top-down design method of programmable logic devices is the most commonly used design method in digital system design and is also the main method of chip-based system design. It first starts with system design, carries out functional division and structural design at the top level, uses hardware description language to describe the high-level system, and uses simulation methods at the system level to verify the correctness of the design, and then designs the low-level structure layer by layer. Since high-level design has nothing to do with devices and processes, and software simulation can be used to verify the feasibility of the system solution before chip design, the top-down design method is conducive to early detection of structural design errors and avoids unnecessary Repeat the design to improve the one-time success rate of the design.

4 Time division multiplexing principle

Time division multiplexing (TDM) divides the channel into several time slots, and each user occupies other channel capacity. TDM provides each user with a time slot that can be rotated among accessing users. TDM periodically scans multiple access points for input signals (input data). Bits, bytes or blocks of data are separated and interleaved into frames and transmitted over a high-speed communications line.

Using the frame format shown in Figure 1, three low-speed signals can be combined into one high-speed signal in a fixed time division multiplexing manner.

5 Introduction to Mux+plus Ⅱ

Mux+plus Ⅱ is a fully integrated, easy-to-learn and easy-to-use visual development tool software launched by Altera Corporation. It has an industry-standard EDA interface and can run on a variety of operating platforms.

The design input method of Mux+plus II is very flexible. Graphic Editor file, Symbol Editor file, Text Editor file and Waveform Editor file can be created according to the design content. ), and can realize the design function. After successful compilation and simulation, the user's own symbols can be generated and stored in the user symbol library for reference in upper-level designs.

6 Design implementation and simulation

This design is divided into three major levels. The top level is the reuse level (as shown in Figure 2). It consists of several sub-level modules. After successful simulation, an independent default symbol (as shown in Figure 3) and a design structure diagram (such as Figure 4). Each sub-layer module in the top-level module can complete a relatively independent function. For example, one of the sub-layer modules can complete synchronization flag insertion and convert the input signal into 8-bit parallel data (as shown in Figure 5). The sub-module is in After successful debugging, it can be generated as a default symbol for the upper layer module to call. The sub-module can be subdivided into several sub-modules, each sub-module can also complete relatively independent functions..., nested in this way, it can be refined to the logic gate level according to actual needs. Each layer can be simulated in time after the design is completed. Figure 6 shows the top-level design waveform simulation diagram.

Mux+plus II design software can also provide automatic selection of devices. That is, after the entire design is completed, the user only needs to provide the device series (such as FLEX 10K) to the software, and the software can automatically select the specific device suitable for this design. If there is no If the device is suitable, the software will prompt the user to reselect. This feature can provide great convenience for users' specific designs.