Application of FPGA in multi-ary orthogonal spread spectrum communication system

    Abstract: This paper discusses the design and implementation of multi-ary orthogonal spread spectrum communication system in high-speed wireless packet network. Many functions such as spread spectrum coding, modulation and demodulation in the core part of the system are completed by FPGA, and this is done detailed introduction.

    Keywords: FPGA spread spectrum communication multi-ary orthogonal spread spectrum QPSK modulation   

    Gate array logic circuits are widely used in digital system design. Therefore, from GAL, EPLD to the current FPGA (field programmable gate array), the capacity, function and reliability have been greatly developed. The current FPGA structure adopts the bus method, and the layout and wiring are convenient and flexible. Altera's FLEX10K series FPGA buries RAM blocks with input and output registers, making it more convenient to apply to CPU systems. As devices develop, the development environment is further optimized. Altera's Maxplus II provides users with a good development environment, containing rich library resources, which makes it easy to implement various circuit designs and complete more complex operations, and hardens part of the software, which is very effective for high-speed systems. . It supports a variety of input methods and has a powerful simulation system to support your arbitrary design. The biggest advantage is that it supports online debugging, which greatly improves efficiency for those who have been engaged in circuit design and debugging for a long time.

    As an important form of wireless packet communication, packet wireless network has been receiving widespread attention in the fields of military and civilian communications. The rapid development of information technology has put forward higher requirements for packet wireless networks, which require higher information rates, support for integrated services, and strong anti-interference performance. To meet these requirements, new technologies must be used to design a new generation of packet wireless terminals. We proposed a method of using multi-ary orthogonal spread spectrum to achieve high-speed (256kbps and 512kbps) safe and reliable communication, proposed new design ideas and adopted a series of new technologies. Application of Altera's FLEX10K series FPGA to achieve multi-ary Orthogonal spread spectrum coding, fast Hadamard transform method, timing control logic and other functions greatly simplify the system. This article discusses the system principles and FPGA applications.

    1 Implementation of multi-ary spread spectrum coding

    1.1 Composition of orthogonal spread spectrum system

    Taking into account factors such as system bandwidth, communication rate, and implementation complexity, we decided to use a hexadecimal orthogonal spread spectrum scheme, and used the Walsh function as the spread spectrum orthogonal code. The information rate is divided into two levels, and the function periods are 64. (low speed) and 32 (high speed). The autocorrelation characteristics of the Walsh function are poor and synchronization acquisition is difficult. We propose a new method of adding an auxiliary synchronization logical channel based on the original multi-ary orthogonal spread spectrum. The m sequence is selected as its spreading code, and the synchronization channel signal is modulated to a carrier frequency orthogonal to the information channel. Figure 1 shows the schematic block diagram of the modulation part. The transmitted data undergoes serial-to-parallel conversion to group every 4 bits of information into one group, completing the 2-to-16 hexadecimal conversion. The I channel transmits synchronization control and auxiliary information (pilot channel) and uses m-sequence modulation. The Q channel transmits data information (information channel) and uses the Walsh function encoding. The I and Q branches perform orthogonal modulation respectively, and the QPSK modulated intermediate frequency signal is synthesized and sent to the radio station.

    1.2 Orthogonal spread spectrum coding rules

    It has been introduced earlier that the synchronization code and the information code are spread using the m sequence and the Walsh function respectively. If implemented according to the given block diagram, a multiplier must be added, which increases the complexity of the system. Look-up table coding is favored by people because of its advantages such as fast, simple and convenient, so the storage look-up table method is used for coding. The selected m sequence with a period of 64 and 16 kinds of Walsh functions (32 bits/64 bits) are bit-interleaved according to the I and Q branch order to form data and stored in EPROM, and then based on the synchronization information and data information as the address Look up the table. Each bit of the synchronization branch corresponds to an m sequence with a period of 64. When the information branch is at low speed, the 64-bit Walsh function is the same length as the synchronization branch code, but when it is at high speed, the 64-bit synchronization code is interleaved with two 32-bit Walsh functions in sequence. Therefore, one address is needed for parity control. According to the above coding rules, the rate control bit is specified as the high-order address and the synchronization code is the second-highest address.

    1.3 Implementation of Orthogonal Spread Spectrum Coding

    Figure 2 shows the implementation principle of multi-ary spread spectrum coding. Among them, the frequency division chain forms the low-order address, EPROM chip select line, parallel/serial conversion latch signal and shift signal, and other clock sources. The serial/parallel conversion output forms the information address. The address forming unit mainly controls address selection at two rates and selects different spreading codes. When the speed is low speed, A3=Ax, and Sd0~Sd3 correspond to A4~A7; when the speed is high speed, A3=Sd0, and A7=Ax, used for odd-even positioning, Sd0~Sd3 correspond to A3~A6. The synchronization code generation unit outputs the synchronization sequence of the synchronization branch, which is a 32-bit 0, 1 code and a 48-bit Barker code. The clock control unit generates Barker code and scrambling code enable signals, and sends the clock signal TXC to the terminal when the synchronization code is sent. As can be seen from the figure, orthogonal spread spectrum coding is easily realized using the look-up table method, and complex multipliers are replaced by some timing combination circuits.

    Due to the poor autocorrelation of the Walsh function, the ability to resist multipath is very weak. The anti-multipath capability of spread spectrum communication is completely determined by the autocorrelation capability of the spread spectrum sequence. Therefore, in the case of multipath propagation, directly using the Walsh function sequence to spread spectrum will inevitably cause serious inter-symbol crosstalk. In order to reduce the inter-code crosstalk caused by the Walsh function sequence spread spectrum and increase the confidentiality and anti-interference ability of the system, it is usually multiplied by a long code sequence for scrambling after orthogonal spread spectrum to improve the autocorrelation characteristics of the Walsh function. We use a 24-bit long scrambling code. The CPU loads the 24-bit mask and initial code to the FPGA through the system bus, and then performs dynamic operations with the input data. The scrambled Q branch information and I branch synchronization information are synthesized into a spread spectrum encoded data bit stream for QPSK modulation. We use Altera's FLEX81188-240-2 chip to implement all logic circuits. The internal logic resources occupy about 30%, the I/O pins occupy about 87%, and the wiring resources occupy about 40%. The remaining resources are convenient for system expansion.

    2 Despreading and demodulation of orthogonal spreading codes

    The signal despreading and receiving block diagram is shown in Figure 3. Among them, the FPGA performs multi-ary correlation despreading operation on the Q channel under the control of the synchronous clock received by the I channel, and is the core unit of the receiver circuit. Considering that it is very difficult to perform coherent reception in a high-speed packet wireless network environment, we adopt the best non-coherent reception principle to perform multi-ary orthogonal code despreading operation. Among them, the multi-channel correlation despreading operation part has a complex structure and consumes a lot of resources, so it is the main task of FPGA implementation.

    The multi-ary despreading unit in Figure 3 is the core unit of the receiver and completes the core part of the optimal non-coherent operation. The amount of calculation is large and it is difficult to implement using software methods. After evaluation, we found that using AD's latest DSP device ADSP21062 can only achieve about 1/3 of its computational volume. We used a piece of Altera's FLEX10K100 to implement three solutions for the parallel correlation despreading algorithm: serial FHT method, parallel FHT method, and parallel integration method. Figure 4 is the implementation principle diagram of the parallel FHT scheme. According to statistics, internal logic resources occupy about 70%, I/O pins occupy about 10%, and wiring resources occupy about 60%.

    The receiving and transmitting ends of the system are connected via IF, and the multi-ary orthogonal spread spectrum communication system can correctly despread and demodulate the multi-ary spread spectrum signal modulated by QPSK, proving that the design scheme is correct and feasible.

    In short, the requirement of our project is to design and implement a new generation of packet wireless terminals used in future high-speed packet wireless networks. Support is relatively difficult and a series of new technologies and new devices must be used to achieve this. By applying Altera's latest FPGA products, we make full use of its advantages such as high speed, large capacity, flexible and convenient combination, and use the library resources provided by Altera's Maxplus=II development environment to maximize the use and play of the advantages of FPGA. Not only The system design is greatly simplified and the design cycle is shortened.

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