Application of McBSP Technology in Data Transmission

Abstract: In embedded data transmission systems, the interface between DSP chips and analog/digital converters is often encountered. In order to improve the sampling, transmission speed and accuracy of signals and enhance system reliability, the principle, hardware and software design methods of the multi-channel buffered serial port (McBSP) based on DSP chips as a receiver in data transmission are given. TI's C5000 series fixed-point DSP TMS 320VC5502 chip and TI's 10-bit high-speed serial successive approximation converter analog/digital conversion chip TLV1572 are selected for seamless connection. The analog data is sampled by TLV1572, then converted into digital signals by A/D, and received by the DSP's McBSP serial port, realizing real-time data transmission without any conversion. The system design scheme has simple circuits, good reliability, easy implementation and certain versatility.
Keywords: multi-channel buffered serial port; TMS320VC5502; analog/digital converter; data transmission

DSP chips mainly complete the tasks of digital signal acquisition, storage, processing and transmission. The multi-channel buffered serial port (McBSP) is one of the most important data acquisition and transmission devices. It is a typical configurable peripheral. By programming its interface parameters and data format, it can realize seamless connection with external IC chips such as encoders with synchronous serial ports. Here, we will take TMS320VC5502DSP and TLV1572 analog-to-digital converter as examples to introduce the application of DSP's multi-channel buffered serial port (McBSP) in data transmission.

1 Hardware composition
1.1 TMSC320VC5502
DSP chip uses TI's TMS 320 VC5502, which is a high-performance, low-power, fixed-point digital signal processor. It has the following main features:
1) The highest main frequency can reach 300 MHz, and the instruction cycle is 3.33ns.
2) It includes 1 32-bit program data bus, 5 16-bit data buses, and 6 24-bit program address buses. This parallel multi-bus structure enables the CPU to complete a 32-bit program code read, three 16-bit data reads and two 16-bit data writes in one CPU cycle. The 5502 also has two multiplication accumulators, each of which can perform a 17x17 bit multiplication operation in one cycle.
3) Contains 28kx16bit on-chip ROM, including 64kBytes of DARAM (8 blocks, 4 kx16 bits each), 192 kBytes of SARAM (24 blocks, 4 kx16 bits each), 64 kBytes of one-wait on-chip ROM (32 kx16 bits) and external storage space with a maximum addressable capacity of 8 Mx16 bits. The 16-bit external memory expansion interface can achieve seamless connection with asynchronous memory devices (SRAM, EPROM) and synchronous memory devices (SDRAM).
4) On-chip peripherals include a six-channel direct memory access controller (DMA), three multi-channel buffered serial ports (McBSP), a programmable digital phase-locked loop clock generator, two 64-bit general-purpose timers, a 64-bit watchdog timer, a 64-bit DSP/BIOS counter, an 8-bit/16-bit host interface (HPI), seven general-purpose input and output ports (GPIO) and an external flag output pin (XF), an internal integrated circuit module (I2C), a universal asynchronous receiver/transmitter (UART), and a JTAG emulation interface that complies with the IEEE1941.1 standard (JTAG) boundary scan logic.
1.2 McBSP (multi-channel buffered serial port)
The TMS320VC5502 DSP provides three high-speed multi-channel synchronous buffered serial ports (McBSP), allowing the TMS320VC5502 DSP to directly interface with other C55x DSPs, multimedia digital signal codecs, and other devices in the system. The serial port provides full-duplex communication; double buffered data registers, allowing continuous data streams to be transmitted; independent transmit and receive clock and frame signals; can be directly connected to industrial standard codecs, analog interface chips and other serial A/D, D/A chips; can receive and transmit 128 channels; has a programmable sampling rate generator; can send interrupts to the CPU and send DMA events to the DMA controller; can set the polarity of the frame synchronization pulse and clock signal; the word length of the transmission can be 8 bits, 12 bits, 16 bits, 20 bits, 24 bits or 32 bits; the McBSP pins can be configured as general input and output pins. The McBSP structure diagram is shown in Figure 1, which can be divided into two parts: data channel and control channel.

The data transmission pin DX is responsible for data transmission, the data receiving pin DR is responsible for data reception, and the transmission clock pin CLKX, the reception clock pin CLKR, the transmission frame synchronization pin FSX and the reception frame synchronization pin FSR provide serial clock and control signals. The CPU and DMA controller communicate with McBSP through the peripheral bus. When sending data, the CPU and DMA write the data into the data transmission register (DXR1, DXR2), then copy it to the transmission shift register (XSR1, XSR2), and output it to the DX pin through the transmission shift register. Similarly, when receiving data, the data received on the DR pin is first shifted to the reception shift register (RSR1, RSR2), then copied to the reception buffer register (RBR1, RBR2), and RBR then copies the data to the data reception register (DRR1, DRR2), and notifies the serial port event to notify the CPU or DMA to read the data. This multi-level buffering method enables on-chip data communication and serial data communication to be carried out simultaneously.

1.3 TLV1572
A/D converter uses TI's 10-bit high-speed serial successive approximation A/D converter, which uses a single voltage of 5 V and has a maximum sampling rate of 1.25 Msps. It can be seamlessly connected to the TMS320 series DSP through McBSP (Multi-channel Buffered Serial Ports). TLV1572 has a sampling rate of up to 1.25 Msps, 10-bit resolution, a single voltage of 3 to 5V, low power consumption (8 mW at 3 V, 25 mW at 5 V), automatic power saving function (maximum current of 10μA), and internal sample and hold function. The functional module diagram of TLV1572 is shown in Figure 2.

TLV1572 has two working modes, namely DSP mode and microcontroller mode. These two working modes are determined by the level of its P3 (frame synchronization input signal). If the FS pin is connected to the power supply VCC and is always high, the TLV1572 works in the microcontroller working mode; if the TLV1572 is in the DSP working mode, the FS pin is either provided by the frame synchronization signal (FSR) of the MCBSP of the TMS320 DSP or introduced from outside the system.
1.4 Connection between TLV1572 and the McBSP buffer serial port of the DSP The connection
between TLV1572 and the serial port of the TMS320VC5502 DSP is shown in Figure 3.

TLV1572 works in DSP mode, and its typical timing diagram is shown in Figure 4.

When working in DSP mode, when the chip select signal /CS of TLV1572 A/D goes low, FS must also be low, and in order to ensure the correct locking of TLV1572 DSP mode, the FS signal level must be detected twice, once at the falling edge of /CS (that is, the FS setup time for the falling edge of /CS, the minimum is 6 ns), and once immediately after an internal delay detection relative to the falling edge of /CS (that is, the FS hold time for the falling edge of /CS, the minimum is 9 ns). In summary, in order to ensure that TLV1572 can be correctly locked in DSP mode, FS must be maintained for at least 15ns after /CS goes low.
After ensuring that TLV1572 works in DSP mode, that is, the low level of FS must be maintained for at least 15 ns, TLV1572 A/D must detect the level state of FS at the falling edge of each SCLK clock signal. Once FS becomes high, it means that A/D enters the reset state. Then when FS becomes low, TLV1572 waits for DSP to latch the first 0. Here, the rising edge of FS has a FS setup time (at least 10 ns) for the falling edge of SCLK, and then corresponding to the falling edge of this SCLK, FS has a hold time (at least 4 ns). FS can only become low after meeting at least the above 14 ns.
Sampling starts from the first falling edge of SCLK after FS becomes low, and continues until the rising edge of SCLK when the sixth 0 is output. At this rising edge of SCLK, the conversion begins and the corresponding converted data is output. There is a 1-bit delay here, and the DSP samples the converted data at the falling edge of SCLK. The data converted by TLV1572 has 6 leading 0s, followed by the converted 10-bit data output from high to low. That is to say, TLV1572 requires 16 SCLKs for a complete conversion of data once. If FS is detected to be high at the falling edge of the 16th SCLK clock, the next new data sampling and conversion will start at the next SCLK, that is, the 17th SCLK, so that the continuous conversion of data by TLV1572 is realized.

2 Software composition
When the transmitted signal is input from the analog signal input terminal of TLV1572, TLV1572 samples the input signal and transmits the sampled data to DSP. The program mainly includes initializing DSP and buffering serial port McBSP, configuring McBSP as a receiver, including resetting the receiver of MeBSP, programming the register of McBSP as needed, enabling the receiver, starting A/D, collecting data and storing it. The process is shown in Figure 5.

When operating the McBSP of the DSP, the output clock CLKG of the internal sampling rate generator of the McBSP is driven to CLKR, and CLKR is also provided to the SCLK of the A/D. The clock source (CLKSRG) of the sampling rate generator of the McBSP is provided by the CPU, and the CPU clock is divided to generate CLKG. Since the clock polarity of the CPU is always positive, the rising edge of the CPU clock signal generates the rising edge of CLKG. After programming the register of the sampling rate generator, wait for 2 CLKSRG (clock source) cycles to ensure internal synchronization. When the sampling rate generator is enabled, wait for 2 CLKC cycles to ensure stable operation of the sampling rate generator. At the next rising edge of CLKSRG, CLKRG becomes 1, starting the clock with a frequency as shown in formula (1).

For the serial port, the frame synchronization signal (internal FSR) is an internal signal and is valid at a high level. If the serial port is configured for external frame synchronization (FSR input to McBSP), and FSRP = 1 (receive frame synchronization signal is active low), then the external active low signal must be converted before it is sent to the receiver (internal FSR). When the McBSP FSR is input, the McBSP detects this FSR signal on the falling edge of CLKR. The received data arriving at the DR pin is also sampled on the falling edge of the internal CLKR. The internal clock CLKR here is driven by the sample rate generator clock (CLKG) and is sent internally to the McBSP.
The receiver can reliably sample the incoming data on the rising edge of the clock. The polarity of the receive clock (CLKRP) is set to the edge used to sample the received data. Note: The McBSP always samples data on the falling edge of the internal CLKR, so if CLKRP = 1 and the internal clock is selected (CLKRM = 1), the internal falling edge triggered clock must be converted to a rising edge triggered clock before it is sent to the CLKR pin output.
The communication between the DSP's CPU or DMA controller and the McBSP is achieved by accessing the internal peripheral bus through a 16-bit register. The McBSP has two data receiving registers, DRR1 and DRR 2. DRR1 is used when the word length is less than 16 bits. The serial word to be transmitted by the McBSP is defined as 16 bits (just the 6 0+10-bit binary numbers from the 10-bit A/D conversion data), and a frame of data transmitted by the McBSP is defined as 16 bits. In this way, after the McBSP receives a frame of data, it triggers an interrupt to store this frame of data, and then performs sampling, conversion and transmission of the next frame of data until the data transmission and acquisition are completed.
The following are the operations to be performed when the MeBSP is configured as a receiver.
1) Global settings include setting the receiver pin to the McBSP pin, enabling or disabling the digital loopback mode, enabling or disabling the clock stop mode, and enabling or disabling the multi-channel selection mode.
2) Data setting means selecting whether each received frame is single-segment or double-segment, setting the received word length, setting the frame length, using or prohibiting the function of ignoring the received frame synchronization, setting the received compression and expansion mode, setting the received data delay, setting the received data expansion and verification mode, and setting the received interrupt mode.
3) Frame synchronization setting means setting the received frame synchronization mode, setting the received frame synchronization polarity, setting the frame synchronization period and pulse width of the sampling rate generator.
4) Clock setting means setting the received clock mode, setting the received clock polarity, setting the clock division value of the sampling rate generator, setting the clock synchronization mode of the sampling rate generator, setting the clock mode of the sampling rate generator (selecting the input clock), and setting the polarity of the input clock of the sampling rate generator.
The software used for debugging the program is TI's Code Composer Studio (CCStudio), which is an integrated software development environment developed by TI for TMS320 series DSP software design. The McBSP initialization program is as follows:



3 Conclusion
Taking the TMS320VC5502 DSP chip and the TLV1572 analog-to-digital conversion chip as an example, this paper discusses in detail the hardware interface and software design of the multi-channel buffered serial port (MeBSP) communication between TLV1572 and DSP. The design scheme is simple and easy to implement, and has certain versatility. According to the needs, the appropriate data processing program code can be embedded in the interrupt service subroutine to form a complete data acquisition and transmission program. The data collected in this article is stored in the RAM inside the TMS320VC5502 chip. Since the external memory interface (EMIF) of the TMS320VC55x DSP supports 8bi-t, 16 bit, and 32 bit data access, and provides a seamless interface for asynchronous memory, synchronous burst SRAM, and synchronous DRAM, if the system needs to collect a large amount of data, the memory can also be expanded through the EMIF interface.