Stepper motor microstepping driver chip A3977 with built-in decoder

1 Introduction
　　
As microstepper motors are increasingly used in applications, their drive circuits are also developing rapidly. Various control chips are becoming more and more functional and easier to operate. A3977 is a newly developed micro-stepper motor drive integrated circuit specially used for bipolar stepper motors. It integrates stepper and direct decoding interfaces, forward and reverse control circuits, dual H-bridge drivers, and current Output 2.5A, maximum output power can be close to 90W. Its main design features include: automatic mixed-mode current attenuation control, PWM current control, synchronous rectification, low output impedance DMOS power output, full, half, 1/4 and 1/8 step operation, HOME output, sleep mode and Easy-to-implement stepping and direction interfaces, etc. Its application circuit structure is simple, easy to use and control, and has extremely wide application value.

2 A3977 operating characteristics
　　
Most microstepper motor drivers require some additional control lines to set the reference value for the PWM current regulator through the D/A converter and complete current polarity control through the phase input. Many retrofit drivers still require some input to adjust the PWM current control mode to operate in slow, fast or mixed decay modes. This requires the system's microprocessor to bear an additional 8 to 12 input terminals that rely on D/A conversion processing. If a system requires so many control inputs and its microprocessor stores the timing tables that implement its control, this increases the cost and complexity of the system.

A3977 can simplify these functions through its unique decoder, as shown in Figure 1. Its simplest step input only requires two input lines: "STEP" (step) and "DIR" (direction). , the output is completed by dual H-bridges of DMOS. Simply inputting a pulse through the "STEP" pin can make the motor complete one step, eliminating the need for phase sequence tables, high-frequency control lines and complex programming interfaces. This makes it more suitable for applications where there is no complex microprocessor or where the microprocessor is overburdened. At the same time, the internal circuit of the A3977 can automatically control its PWM operation to work in fast, slow and mixed attenuation modes. This not only reduces the noise generated by the motor during operation, but also eliminates some additional control lines.
　　
In addition, its internal low output impedance N-channel power DMOS output structure can make its output reach 2.5A, 35V. Another advantage of this structure is that it can complete the synchronous rectification function. Due to the synchronous rectification function, it not only reduces the power consumption of the system, but also eliminates the need for additional Schottky diodes in applications.

The sleep function of A3977 can minimize the power consumption when the system is not working. Most of the chip's internal circuits, such as output DMOS, comparators and charge pumps, will stop working during sleep. Therefore, in sleep mode, the total current consumption, including motor drive current, is within 40μA. In addition, the internal protection circuit also has functions such as thermal shutdown, low-voltage shutdown and commutation protection using hysteresis.

The main features of the integrated circuit:
　　(1) Rated output: ±2.5A, 35V.
　　(2) Low output impedance, 0.45Ω at the source end and 0.36Ω at the receiving end.
　　(3) Automatic current decay detection and selection of mixed, fast and slow current decay modes.
　　(4) The logic level range is 3.0~5.5V.
　　(5) HOME output.
　　(6) Synchronous rectification function to reduce power consumption.
　　(7) Internal low voltage shutdown, thermal shutdown circuit and circulation protection.

3 A3977 pin description
　　
A3977 has two packages: one is a 44-pin copper-labeled plastic package (suffix: ED, A3977SED), and the other is a 28-pin plastic package with a thermal pad (suffix: LP, A3977SLP). The pin function description is shown in Table 1.

Charge pumps CP1 and CP2 can generate a gate level higher than VBB to drive the DMOS source gate. The implementation method is to connect a 0.22μF ceramic capacitor between CP1 and CP2. At the same time, a 0.22μF ceramic capacitor is also required between VCP and VBB as an energy accumulator to operate high-end DMOS equipment.
　　
VREG is generated internally by the system and is used to operate the DMOS drain output. The VREG pin must add a 0.22μF ceramic capacitor to ground as an energy accumulator to operate high-end DMOS equipment.
　　
VREG is generated internally by the system and is used to operate the DMOS drain output. The VREG pin must be decoupled with a 0.22μF capacitor to ground. VREG is controlled by an internal level regulator, and its output is disabled when a fault occurs.
　　
The RC1 and RC2 pins provide fixed cutoff times for the internal PWM circuit. The internal PWM control circuit of the A3977 uses a pulse to control the cut-off time of the device. The -84- cut-off time toff of this pulse is determined by the resistor RT and capacitor CT connected to the ground between the RC1 and RC2 pins, that is:
　　
　　toff = RT CT
　　
　　. In the formula, the value ranges of the resistor RT and capacitor CT are respectively 12～100kΩ and 470～1 500pF>
　　
　　In addition, in addition to providing cut-off time for internal PWM control, CT also provides off-time tBLANK for the comparator. The design of the A3977 requires that the output of the circuit sampling comparator be disabled when its output is switched by the internal current control circuit. This prevents misjudgment of overcurrent detection. The value of tBLANK is:
　　
　　tBLANK=1400CT
　　
　　ENABLE input is active at low level, which is the enable control signal of DMOS output. The RESET input is also active low. When it is low, the output of DMOS will be turned off and all step logic inputs will be ignored until its input goes high.

4 Basic Function Description and Application Circuit
　　
Due to the use of built-in decoder technology, A3977 can easily implement micro-stepping control of the stepper motor using the least control lines. The specific functions are implemented as follows:
　　
　　(1) Step control: The step control signals include step input (STEP), step mode logic input (MS1, MS2) and direction control signal (DIR). After each power-on or reset (RESET=0), the output of the H-bridge is preset to the output state corresponding to the HOME input under the action of the built-in decoder. Then when the rising edge of the STEP input arrives, the built-in decoder The device will control the output of the H-bridge according to the input value of the step logic (see Table 2 for step mode), so that the motor will generate one step in the current step mode.
　　
　　The direction of the step is controlled by the input logic of DIR, and its high and low levels control the forward and reverse rotation of the two-phase motor respectively.

　　Note: ①The angle of full step rotation is 45°.
　　
　　(2) Internal PWM current control: Each H-bridge has a PWM current control circuit with a fixed cut-off time to limit its load current to a designed value. Initially, a pair of source-receiving DMOS (a pair of upper and lower bridge arms) on the diagonal line are in the output state, and the current flows through the motor winding and the current sampling resistor connected to the SENCE pin (see Figure 1). When the voltage drop on the sampling resistor is equal to the output voltage of D/A, the current sampling comparator resets the PWM latch, thereby turning off the source driver (upper arm) and entering the slow attenuation mode; or turning off the source receiving driver at the same time (The upper and lower bridge arms) enter the fast or mixed attenuation mode, causing circulating current or current to flow back to the source. This circulation or backflow will continue to decay until the end of the fixed cut-off time. Then, the correct output leg is enabled again, the motor winding current increases again, and the entire PWM cycle is completed.
　　
　　Among them, the maximum current limit Imax is controlled by the sampling resistor RS and the input level VREF of the current sampling comparator:
　　
　　Imax=VREF/8RS The calculation of the fixed cut-off time tooff is as described above.
　　
　　(3) Current attenuation mode control: A3977 has the function of automatically detecting current attenuation and selecting current attenuation mode, thereby providing the best sinusoidal current output for micro-stepping. The current attenuation mode is controlled by the input of the PFD, and the input level controls the output current in slow, fast and mixed attenuation modes. If the input voltage of the PFD is higher than 0.6VDD, the slow decay mode is selected. If the input voltage of the PFD is lower than 0.21VDD, the fast decay mode is selected. PFD level values ​​in between will select mixed attenuation mode.
　　
　　The mixed decay mode divides the fixed cut-off time of a PWM cycle into two fast and slow decay parts. When the current reaches the maximum current limit Imax, the system will enter the fast decay mode until the sampling voltage on SENCE decays to the terminal voltage VPFD ​​of the PFD. After the fast decay of tFD, the device switches to slow decay mode until the end of the fixed cut-off time.

　　Among them, the time tFD when the device works in the fast decay mode is:

　　tFD=RTCrln (0.6VPFD/VPFD)
　　
　　(4) Synchronous rectification control: Synchronous rectification control is controlled by the logic input of SR. When the SR input is low, the synchronous rectification function will be enabled. During this period, when the current is detected to be zero, the synchronous rectification function can be turned off to prevent the load current from being reversed, thereby preventing the motor winding from conducting in the opposite direction. When the SR input is high, synchronous rectification will be disabled.
　　
　　(5) Sleep mode: When the SLEEP pin input is low, the device will enter sleep mode, thereby greatly reducing the idle power consumption of the device. After entering sleep mode, most of the device's internal circuits, including DMOS output circuits, regulators and charge pumps, will stop working. When its input is high, the system returns to normal operation and presets the device's output to the HOME state.
　　
　　(6) Typical application circuit: Its typical application circuit is shown in Figure 1. It can be seen that its application circuit is very simple and only requires 5 logic inputs during normal operation.

5 Application Notes

　　(1) A 0.1μF capacitor should be added to the PFD introduction end for decoupling.　　
　　(2) A thicker ground layer should be laid when wiring. It is best to lay a star ground around the device.
　　(3) It is best to solder the chip directly to the circuit board.
　　(4) Add an electrolytic capacitor greater than 47μF to the VBB pin for decoupling (the closer to the chip, the better).
　　(5) In order to ensure the accuracy of output current sampling, it is best to have the sampling resistor have its own separate ground and connect it to the star
ground , and the shorter the lead, the better.
　　(6) When the system exits from sleep mode, there must be a delay of at least 1ms before the step command can be input, thereby providing sufficient time for the charge pump driving DMOS to reset.