1 Structural features of the EPM7032 device
1.1 Structure of EPM7032 device
The programmable logic device EPM7032 is based on Altera's second-generation multi-array matrix (MAX) structure and is manufactured using advanced CMOSEEPROM technology. The device consists of a logic array block (LAB), a programmable wiring array (PIA) and an I/O control block. Its structure is shown in Figure 1.
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Each logic array block in the EPM7032 consists of 16 macrocell arrays, in which multiple logic array blocks are connected together through a programmable wiring array. The PIA global bus can be fed by all dedicated inputs, I/O pins and macrocells. The macrocells of the EPM7032 can be individually configured to operate in sequential logic or combinational logic. Each macrocell is composed of three functional blocks such as logic array, product term selection matrix and programmable register.
Each LAB can be connected to each other through a programmable wiring array to form the required logic. At the same time, any signal source in the device can also be connected to its destination by routing on the PIA.
The I/O control block allows each I/O pin to be individually configured as input, output, and bidirectional operation. All I/O pins have a tri-state buffer. They are controlled by two dedicated active-low output enable pins OE1 and OE2.
1.2 Performance characteristics of EPM7032 device
The main features of the programmable logic device EPM7032 are as follows:
●The logic density is 600 available gates;
●The EPM7032 device can 100% imitate TTL, and can integrate the logic functions of SSI, MSI and LSI at a high density. It can also integrate from PAL , GAL, 22V10 to MACH and PLSI devices, a variety of programmable logic devices;
●The pin-to-pin logic delay is 5.0ns, and the counter operating frequency reaches 178.6MHz;
●The programmable macrocell flip-flop has dedicated clear, Set, clock and clock enable control;
●Programmable extended product term allocation allows up to 32 product terms to be provided to each macrocell;
●Power supply voltage is 3.3V or 5.0V;
●Comply with PCI regulations;
● The CMOSEEPROM unit is used to implement logic functions, which can realize a variety of independent combinational logic and sequential logic functions. During the design, development and debugging stages, the device can be quickly and effectively programmed repeatedly;
●Online programming can be achieved through the JTAG interface , and can guarantee programmable erasure for more than 100 times;
●With programmable security bits, it can fully protect the patented design;
●Altera's MAX+PLUSⅡ (Multiple ArrayMatrix and Programmable Logic User System) development system can provide software design support for the device .
2 Design and implementation of automatic traffic control system
2.1 Design of automatic traffic control system
This design adopts the top-down (TOP-TO-DOWN) design method. This method is a hierarchical and modular design method that gradually refines from abstraction to concreteness and from high level to low level. It is the most commonly used design method in digital systems and is also a system design method based on complex programmable devices. main methods of design. This method first plans the functions and performance of the entire system as a whole, and then divides the system to decompose it into smaller-scale, simpler-function local modules and determine their interrelationships. This division process can continue until the units obtained by division can be mapped to the physical layer.
This article introduces how to use this method to design digital systems through the specific design of automatic traffic control systems. This design method is also suitable for the design of complex digital systems.
Traffic lights at intersections direct the safe operation of pedestrians and various vehicles. Realizing automatic command of traffic lights is an important issue in urban traffic management automation. The working process of the automatic traffic control system designed in this design is: Under normal circumstances, if there are no vehicles required to pass on both the main road and the branch road, it should be ensured that the green light on the main road is on and the red light on the branch road is on. At this time, if there are vehicles on the branch road that require passage, the vehicles on the branch road should be allowed to pass; if there are vehicles on both the main road and the branch road that require passage, the main road should be allowed to pass for 30 seconds before allowing the branch road to pass. Before allowing vehicles on branch roads to pass, the yellow light on the main road should be on for 5 seconds. The red light on the branch road should remain on for 5 seconds, then the red light on the main road should be on, and the green light on the branch road should be on at the same time. When the branch road remains open, if no vehicles are required to pass on the main road, the branch road will always remain open; if no vehicles are required to pass on the branch road at this time, preparations should be made immediately to open the main road to traffic, and the branch road is closed to traffic; if the main road is closed to traffic at this time, If there are vehicles on the road that require passage, and the passage time of the branch trunk road has exceeded 20 seconds, preparations should be made to allow the main trunk lane to pass. Before allowing traffic on the main road, the yellow light on the branch road should be on for 5 seconds. After the red light on the main road remains on for 5 seconds, the green light on the main road should be on, and the red light on the branch road should be on at the same time.
The system block diagram derived from this working process is shown in Figure 2. The function of the sensor part is to detect whether there are vehicles on the main and branch roads that require passing through the intersection through sensors installed on the main roads and branch roads. The signals sent by the sensors on the main and branch roads are represented by Sa and Sb respectively. Sa and Sb are '1', indicating that there are vehicles requiring passage, otherwise there are no vehicle requirements. The clock circuit is used to provide a stable clk second pulse signal to the system for timing and system synchronization control. The timer circuit completes the timing function under the action of the timing signal cnt and clear signal cr provided by the controller, and provides timing signals of 5s, 20s and 30s to the controller. The design of the controller is the core of this system. Its function is to judge, adjust and control the status of the entire system based on the signals provided by the sensor and timer, control the work of the timing circuit, and provide appropriate lighting control signals. Among them, the signals that control the red, yellow, and green lights on the main and branch roads are represented by R, Y, G and r, y, g respectively; a value of '1' means the light is on, and a value of '0' means the light is off.
The automatic traffic control system is actually a control-type digital system. The detailed algorithm flow chart of the system based on its working process is shown in Figure 3.
Figure 3 Automatic traffic control system algorithm flow chart
2.2 Implementation of automatic traffic control system
The development environment of this design adopts Altera's MAX+PlusⅡ software tool. MAX+PLUSⅡ is a fully integrated, easy-to-learn and easy-to-use programmable logic design software that integrates design input, compilation, simulation, synthesis, device programming and other functions. The software allows designers to freely choose design input methods and tools. Designers do not need to understand the complex internal structure of the device in detail, but only need to select the design methods and tools they are familiar with for design input. The software provides a truly structure-independent programmable logic design environment, which supports devices of different structures, such as FLEX, MAX and CLASSIC series devices. In this way, the VHDL source file can be easily designed according to the algorithm flow chart, and then input into the MAX+PlusII software for debugging and simulation. The simulation results are shown in Figure 4. The correctness of the design can be verified through functions such as simulation waveforms and timing analysis, and the design can be quickly modified without changing the hardware circuit, thus greatly shortening the design cycle and improving efficiency. After confirming that the design is correct, the generated configurable file can be loaded into the programmable logic device EPM7032 through Altera's programming cable ByteBlaster, and then the entire design can be completed through debugging.
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Figure 4 Automatic traffic control system simulation waveform diagram
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