The Principle and Structure of the Workstation System with TMS320C32 Chip

How to combine the big data space and high computing power of PC system with the miniaturization of single-chip microcomputer, DSP devices provide a good solution. DSP devices are high-performance processing devices designed for digital signal processing. They have been widely used in many fields such as communication, image processing, and medical treatment. Moreover, with the development of large-scale integrated circuit technology, their cost performance ratio has also been greatly improved. This paper introduces a real-time ECG signal acquisition system with DSP TMS320C32 chip as the core.

At present, the ECG workstation system, which mainly focuses on automatic measurement, analysis and diagnosis of ECG signals, has been widely used, and has played a great role in the early prevention and real-time diagnosis of heart diseases. The following characteristics can be found by analyzing the traditional ECG workstation system: 1) Most of them are based on PC systems, and the ECG signals are stored on the PC through the PC sampling interface card, and then analyzed and processed by the PC, which is inconvenient to use for data collection in some occasions (such as at the patient's bedside or at home); 2) The single-chip microcomputer is used to make a small instrument that can be carried around, but due to the limited computing power and data space of the current 8/16-bit single-chip microcomputer system, it is powerless for some long-term data collection or signal processing that requires more complex algorithms.

2 System Structure

2.1 Features of TMS320C32

TMS320C32 is a new generation of floating-point C3X series DSP devices from TI of the United States. It simplifies and improves C30 and C31 and has the following features:

1) With an external 40 MHz crystal oscillator, it has a computing speed of 40 MFLOPS, 20MIPS, 32-bit computing accuracy, a powerful instruction system, and all instructions are executed in a single cycle;

2) Rich hardware resources, including 1 serial port, 2 clocks, 2 DMA control channels, priority can be set, 4-level priority interrupt, support for multiple addressing modes, and improved signal processing computing capabilities;

3) Large addressing space, 24 address lines have nearly 16 Mb of space, the width of the data program bus is variable, STRB0, 1 can be defined as 8/16/32 bits of data width and external memory width;

4) The external interrupt trigger mode can be selected as level/edge mode, the internal interrupt vector table address can be reset, and the program boot can be realized by the chip's internal Boot Loader;

5) Added two power-saving operation modes, low power consumption.

2.2 Main design indicators of the system

The following is a design block diagram of the ECG data acquisition system with DSP as the core, as shown in Figure 1, which mainly includes the following features:

1) Multi-channel signal sampling, which can control the analog multiplexer to collect 16 signals, including 12 conventional ECG signals, 3 orthogonal CMP signals and 1 heart rate variability signal HRV;

2) The A/D sampling frequency is 16 kHz, the resolution is 12 bit, the conversion accuracy is high, and the linear error is 1/2 LSB;

3) Large storage capacity. 1 Mb of storage space can store multiple channels of long-term ECG data and analyze diagnostic results;

4) There is a programmable logic chip MACH to realize logic control;

5) Other parts include LCD graphic dot matrix liquid crystal display and input buttons.

2.3 Signal acquisition system

2.3.1 Program and data memory

The amount of data collected in real time by multiple ECG signals is relatively large. A conventional 12-channel ECG signal of 10 s has a data volume of 240 k bytes. The system uses a large-capacity fast flash memory as the memory. C32 allows a variable width external memory interface. When used for data storage, the width can be 8/16/32 bits, and when used for program storage, the width can be 16/32 bits. Therefore, a 16-bit external memory interface is designed to store both application programs and data. Two Atmel27F080s form a 1Mb×16 memory, using a 16-bit memory interface to reduce the size of the system. The data storage time of Atmel 27F080 is 70 ns, which meets the requirements of a fast interface and allows the storage and erasure of data at any location. The connection with the DSP is shown in Figure 2.

The internal RAM of DSPC32 is 512 words. To enhance its algorithm processing capability, an external 32 kb high-speed SRAM is added, which is composed of 4 ISSI61C256-15 chips and has a storage speed of 15 ns.

2.3.2 Multi-way switch and A/D signal acquisition

After amplification, the multi-channel ECG signals are input to the A/D converter through the multi-channel analog switch for time-division multi-channel signal sampling. The multi-channel switch uses the Max336 16-channel select 1 switch. Channels 1 to 12 are designed to be used as 12-channel conventional ECG signal inputs, channels 13 to 15 are used for the collection of 3-channel orthogonal signals, and channel 16 is used for the heart rate variability signal input. During the specific collection, the DSP control logic device determines the channel to be collected.

A/D conversion is done by Max196. Max196 can realize 12-bit analog-to-digital conversion, single 5 V power supply, internal reference voltage Vref conversion circuit, support ±10 V, ±5 V, 0-10 V, 0-5 V voltage conversion range, input signal range is determined by control word, A/D conversion rate can reach 100 ksps, low power consumption working mode, input and output pins are all three-state, and the interface with microprocessor is simple, as shown in Figure 3.

DSP writes control words to start A/D conversion. After A/D conversion is completed, Int signal is generated and connected to Int1 of DSP, generating external interrupt and DSP reading conversion result. The sampling frequency of the system is 16k, and the instruction cycle of DSP is 50 ns. Therefore, between two conversions, DSP has enough time to process data, including data filtering and storage.

2.3.3 MACH logic control part

The logic control of the system is implemented by MACH4 64/32 (see Figure 4). MACH4 64/32 is the second generation of high-density, electrically erasable, CMOS PLD device from Vantis, with a logic capacity equivalent to 1250 equivalent PLD gates. In this system, MACH is responsible for generating chip select signals for various peripherals, count control signals for analog switches, key encoding, etc.

When A1A0 assigns the value 00 to the register inside MACH, the output Q3Q2Q1Q0 counts in base 12 from 0000 to 1011, and the analog switch selects the conventional 12-lead ECG signal; when A1A0=01, the output Q3Q2Q1Q0 counts in base 3 from 1100 to 1110, and the analog switch selects the 3-lead orthogonal ECG signal; when A1A0=10, the output Q3Q2Q1Q0=1111, and the analog switch selects the heart rate variability signal.

The system has 4 buttons for function selection. MACH encodes the buttons and determines the button code D1D0. At the same time, a button interrupt signal is generated and connected to the Int2 pin of DSP.

3. Heart rate variability analysis on ECG workstation

Heart rate variability (HVR) analysis has received widespread attention in clinical research and has become a hot topic in cardiovascular disease and electrophysiological research. The general processing method is to collect the R wave interval of short-term (520 points) or long-term (24 hours) ECG signals, analyze them from multiple signal processing perspectives, and give key parameters. The process of heart rate signal acquisition and processing in this system is shown in Figure 5.

The system settings include setting the sampling frequency fs = 1 kHz and selecting the 16th channel with the analog switch. Since the object of HRV analysis is the RR interval of the ECG waveform, the R wave of the waveform is located while the data is sampled, the R wave position is found, and the interval RR interval between adjacent R waves is calculated and stored. The high-speed characteristics of DSP enable more complex signal processing to be performed while data is sampled, and the position of the R wave can be found more accurately. The following measures are adopted:

1) Digital filtering: The sampled signal passes through a low-pass digital filter with a cutoff frequency of 150Hz to filter out high-frequency interference signals in real time.

2) Use the slope tracking method to determine the position of the R wave. A threshold is determined in advance. When the slope of the acquired waveform exceeds the threshold, track and find the position with the largest slope change, that is, the position of the R wave.

After sampling, the RR interval is quickly analyzed. The analysis method includes statistical analysis in the time domain and spectral analysis in the frequency domain. Multiple analysis results are displayed on the LCD.

The ECG workstation system designed in this paper with DSP320C32 chip as the core makes it possible to collect and analyze multiple ECG signals in real time. The system is small in size and easy to carry. It also has strong computing power. Adding digital filtering, neural network and other methods to the analysis program will greatly improve the processing power and diagnostic accuracy. At the same time, by appropriately changing the program (such as the definition of the input signal channel) and the analysis program, the system can also be used for real-time processing of other physiological signals.