DSP power management technology speeds up design progress

Many battery-powered handheld systems require digital signal processing, and when designing such products, power consumption must be a top priority.
Choosing a DSP that has all the necessary computational power while also meeting the design power requirements can make the difference between a successful design or a complete failure, forcing the design team to undergo an expensive redesign.
However, as most designers have learned the hard way, traditional DSP power estimation methods are only approximate at best, so new techniques are needed to manage power consumption and estimate it in software.
Datasheets Are Not Enough
In the past, when design teams selected a processor, they would first look at the datasheet of a candidate DSP. Measurements in mA/MIP or mA/MHz are usually given along with the maximum IDD of the chip. Almost all datasheets provide this information.
The problem with this data is that power consumption is highly dependent on the application itself, and the statistics in the datasheet often do not fully reflect the actual application.
Semiconductor companies recognize this problem and usually only provide a baseline figure for power estimation. For example, a common TI DSP will have the following operating conditions: the CPU performs 75% dual MAC and 25% ADD, with moderate data bus activity (sine wave graph). CPU and CLKGEN (DPLL) domains are active.
Unless the design team's application scenario is consistent with the above description, the datasheet data is only used to compare similar chips from the same manufacturer. In fact, other semiconductor companies are likely to measure power consumption in different situations.
There are also some situations that make the datasheet data more questionable, which makes it more challenging for designers who face strict power constraints.
DSPs are complex chips that include power saving features such as sleep modes and power-down modes. These features will magnify the errors in a single estimate.
The datasheet does not take into account that power consumption actually consists of two parts: the processor operating on the core voltage supply and the peripherals operating on the I/O supply.
Design teams want to compare power consumption with different implementations and platforms.
Due to the above challenges, design teams often need to build prototype boards and estimate power consumption based on different processors, implementations, platforms, etc. The above method, although time-consuming and costly, at least provides us with relatively accurate data.
Variable Measurements
We have a good understanding of the methods used to estimate power consumption under different scenarios and implementations. Only after being broken down and based on actual measurements will the data be more useful. The specific process is usually as follows:
divide the chip into subsystems;
execute each subsystem independently;
use subtraction analysis to determine the power consumption of each subsystem;
determine the maximum power consumption and idle power consumption of each subsystem;
use interpolation to estimate the power consumption of the subsystem; and
finally use superposition to estimate the power consumption of the chip.
We usually put the measured data together with the data provided by the manufacturer (such as core voltage) into a spreadsheet and make estimates through appropriate calculations. As shown in Figure 1, the gray and white part on the right is the power consumption estimate result.

Figure 1. Spreadsheets are useful, but they still don't reflect reality.
This approach, while an improvement over comparing datasheet values, still needs to be improved. For example, let's assume that a DSP used primarily for filtering applications is active about 20% of the time and idle about 80% of the time.
Today's DSPs need to take into account duty cycles, which can help save power. For example, the voltage can be reduced to idle values ​​when the chip is not working. Frequency plays a major role in CMOS power consumption, and if the chip is not involved in filtering, then we can reduce the frequency.
Power Optimization Techniques
Semiconductor manufacturers such as TI have worked hard to introduce chip-level power control techniques. Previously, design teams could not use this feature. Now, designers can take advantage of power optimization techniques through software.
To illustrate how this can be achieved, let's first look at some of the methods that design teams can use to optimize performance.
Within the chip itself, system designers can use techniques such as deep sleep modes, dynamic voltage and frequency scaling, and shut down unnecessary resources when the chip is idle.
We can also save a lot of power during system startup. Generally speaking, the boot process starts all systems, but we can shut down or idle applications and parts that are not used during the boot process.
We also need to consider power consumption when optimizing software code. The general rule is that we should integrate as many necessary functions as possible in the smallest possible footprint, which can reduce the memory area. However, this approach often leads to increased power consumption because the application has to execute the code more frequently.
When writing code, we should also reduce the number of instruction accesses and optimize caches and internal instruction buffers. These measures can help save the DSP's working mode time and maximize idle time, thereby reducing frequency and voltage.
Other techniques that can be used to achieve system-level control include:
Careful component selection
Minimize the number of components as much as possible
Use internal memory first to minimize power loss between chips
Use external memory for startup or slow operations and occasionally used functions
Power off the boot memory after startup
New generation power control technology
Generally speaking, semiconductor manufacturers build power-saving features into chips that work automatically, for example, the voltage and frequency will automatically decrease when the chip enters the idle state.
However, we now have more sophisticated techniques, and system designers can now work on the DSP BIOS to further enhance power management.
Automatic voltage or frequency scaling is a useful feature. However, rapid changes in the DSP core voltage often have unexpected effects on peripherals. The operating system's time base may be affected by frequency changes, and some peripheral drivers may need to be aware of changes in frequency and power states in order to continue to work effectively.
The effectiveness of the operating system scheduler can also be affected by frequency scaling. In general, the system should be coordinated to ensure safe voltage and frequency control and to enter idle states appropriately.
Semiconductor manufacturers have created DSP BIOS power adjustment libraries to achieve more advanced power control while ensuring that problems caused by voltage and frequency scaling are avoided. We can also extend the above control techniques from the chip to the peripherals by sending messages to the peripherals through GPIO pins.

Figure 2 shows an example of a power scaling routine (PSL in the figure below) that the designer can write in code and call directly from a library.

Let's assume that the DSP is running a very complex algorithm. Typically, the core voltage is 1.6V and the frequency is 200 MHz, as shown by the blue line on the left in Figure 2. However, when the algorithm is not running, we can use the Power Scaling Library to reduce the frequency to 72 MHz.
Typically, the core voltage remains at 1.6V. However, we can also use the Power Scaling Library to safely reduce the voltage to 1.2V, thereby further reducing power consumption by 30 mW during the period when the algorithm is not running.
TI pioneered the Power Scaling Library in its TMS320VC5509 A DSP, which is the DSP used in this example. Figure 2. The Power Scaling Library function enables power fine-tuning. Next-generation power estimation techniques In addition to the help of various power tools mentioned above, designers also need to find a way to estimate the power of the entire system. The latest approach to this problem requires integrating software provided by semiconductor companies with hardware provided by virtual instrumentation vendors such as National Instruments. In this approach, developers can use LabView provided by National Instruments to monitor the execution of the chip during the actual application. TI provides extensive power test data for the TMS320VC5509 in the data sheet. Using LabView and the C55 Power Optimization DSP Starter Kit, the design team can try different implementations and tune power consumption using a GUI tool similar to the one shown in Figure 3.

Figure 3. Tuning DSP core, I/O, and board power consumption.
The toolkits described above allow you to explore various design scenarios and measure the power consumption of the DSP core, DSP I/O, and the entire board including flash memory, codecs, and other peripherals with high accuracy.
By combining these innovative approaches to controlling chip power consumption and estimating system power consumption, designers gain a powerful new approach for power-critical DSP applications.