A Design of Virtual Instrument Based on PCI Bus and DSP Technology

Traditional virtual instruments consist of a data acquisition board based on the PCI bus that directly utilizes A/D and D/A chips and corresponding software. However, with the rapid development of computer network technology, more and more data needs to be processed, stored and transmitted by computers. Due to the characteristics of general-purpose computers themselves, they are usually not suitable for digital signal processing with high real-time requirements. Therefore, this type of virtual instrument cannot meet the increasingly high requirements of real-time data processing capabilities, data transmission capabilities and data management capabilities put forward by real applications.

At the same time, with the continuous improvement of the cost performance of digital signal processors (DSP), its application areas are rapidly expanding, resulting in the emergence of new virtual instruments based on PCI bus and DSP technology.

Basic framework of the system

The basic framework of the virtual instrument designed by the author based on PCI bus and DSP technology is shown in Figure 1.

The entire system is implemented based on a modular design concept. The development of this system mainly includes the following steps: 1) Design a motherboard based on the PCI bus, which has its own defined bus connectors, as well as the logic control unit and data buffer storage chip of the entire system; 2) Design the data acquisition module and the data output module; 3) Develop the Windows driver for the PCI motherboard so that the PC can normally identify the board and allocate the required system resources; 4) Develop the program for the DSP data acquisition module of the system's lower computer to realize the acquisition of analog signals and the FFT algorithm processing of data; 5) Develop the control software of the system's upper computer PC to realize data waveform display, port configuration, memory reading and writing, and instrument control functions.

Figure 1 The basic framework of the virtual instrument system

System hardware design

As shown in Figure 1, this virtual instrument system first needs a motherboard based on the PCI bus. The board has a custom bus connector that can be plugged into other data acquisition DSP daughter boards based on the bus. In addition, the board also has the logic control unit of the entire system and the data buffer storage chip; other functional modules are implemented based on the expansion board; the storage and transmission of data between modules can be achieved through dual-port RAM. We choose Cypress's 8K×16b high-speed dual-port RAM chip CY7C025V because its timing matches the DSP timing, which is particularly suitable for high-speed bidirectional transmission of large amounts of data between DSP and PC.

1 Implementation of PCI interface

In the design of PCI bus adapter card, a dedicated PCI interface chip is used to implement PCI interface, and the designer does not need to devote energy to the complex PCI interface function design and verification test. The dedicated interface chip can realize the complete PCI master control module and target interface function, and convert the complex PCI interface into a simple interface. In this design, the universal interface chip PCI9052 of PLX company is selected, which contains read and write FIFOs to match the 32-bit, 33MHz PCI bus with the local bus whose bus width may be narrower than it or whose bus speed may be slower than it. PCI9052 has a maximum of 5 local address spaces and 4 chip selects. Figure 2 is the signal interface module diagram of PCI9052.

Figure 2 PCI9052 signal interface

The data source of PCI allocated resources is realized through the external EEPROM. According to the requirements of the PCI9052 interface chip, an EEPROM supporting a three-wire serial interface from Microchip is selected. During power-on, the PCI RST# signal resets the PCI9052 internal registers. The PCI9052 also outputs a local reset signal (LRESET#) and checks whether there is an external EEPROM. If it exists and the first 16-bit word is not FFFFH, the PCI9052 loads the data in the EEPROM into the internal registers of the PCI9052; otherwise, the default value is used. The PCI9052 configuration register can only be written by the EEPROM or the PCI host processor. During EEPROM initialization, the PCI9052 responds to PCI target access with the RETRY signal. Figure 3 shows the connection circuit diagram of the EEPROM (93CS46) and PCI9052 in this design.

Figure 3 Connection circuit diagram of EEPROM and PCI9052

The main information configured in the EEPROM includes: device identification number, vendor code, size of four local bus spaces and base address of the space, etc. The configuration information can be written into the configuration EEPROM in advance through a programmer, or the EEPROM can be operated with PLXMon after the system starts.

2 Implementation of system control logic

Since the CPLD device can save the internal program of the chip after power failure, there is no need for tedious repeated burning, so this design uses Altera's CPLD device as the logic control of the PCI interface chip and storage chip. Considering the need to use 16 local address/data lines and 22 control signal lines, and to reserve some I/O pins for the data acquisition circuit, it was finally decided to use the EPM3128 in the 144-pin TQFP package.

In this system, the main functions of EPM3128 are to realize the address decoding of PCI Local, the address decoding of each DRAM control by DSP Local, and the decoding of the state of the function selection switch on the board, so as to realize the configuration of system functions and the logic decoding of the control signals of each chip. All decoding work is realized by VHDL programming language. The synthesis and compilation work is completed in Altera's QuartusII integrated compilation environment.

3 Implementation of data acquisition circuit

The data acquisition circuit is the key to this system. The quality of the data acquisition circuit design will directly affect the performance of this system. In order to achieve the configurability and scalability of the system function, the data acquisition module is designed in a configurable mode and plugged into the bus interface motherboard to realize the data acquisition of external signals. The data acquisition module consists of a high-speed 16-bit ADC (LTC1608) and a high-performance DSP chip ( TMS320C6713 ). The parallel digital interface of LTC1608 can easily communicate with a variety of DSPs including TMS320C6713, and can be connected to 3V or 5V logic.

Due to the high requirements for acquisition accuracy, before the signal enters the ADC, a series of processing is required on the analog signal to ensure the reliability of the signal: the analog signal first passes through a voltage follower operational amplifier to increase the input impedance, then undergoes voltage proportional amplification and first-order RC low-pass filtering, and finally is input into the ADC.

Figure 4 Schematic diagram of input signal processing circuit

Figure 5 LTC1608 A/D chip pin connection circuit diagram

The specific signal processing circuit is shown in FIG4 and FIG5.

System software design

As shown in Figure 1, after the hardware design is completed, software support is still needed to make the entire system work. The software includes PCI device drivers, data processing algorithm programs, and system control software.

1 Device Driver Design

Device drivers do not exist independently, but are part of the kernel of the relevant operating system, so you need to have a certain understanding of the operating system. Windows 2000 operating system is a 32-bit multi-tasking non-real-time operating system. The operation of the entire system bottom layer and the user's right to interact with the hardware are shielded, and the operating system must uniformly manage device drivers and other kernel access to enable application software to access hardware. When designing and using PCI devices, it is often necessary to access system resources in software, so only by compiling device drivers can you achieve full access to PCI bus devices.

An application makes a Win32 call for device I/O, which is received by the I/O system service. The I/O manager constructs an appropriate I/O request packet (IRP) from this request. In the simplest case, the I/O manager simply passes the IRP to a device driver, which interacts with the hardware and completes the processing of the IRP. The I/O manager returns data and results to Win32 and the user application. It is common for an IRP to be processed by a layered stack of device drivers. Each driver divides the request into simpler requests. The highest-level driver (such as the file system driver) knows how the file is represented on the disk, but does not know the details of how to get the data; the middle-level drivers further process the request; and the lowest-level drivers actually interact with the hardware.

The hardware driver development tool selected for this design is a driver integrated development kit (DriverStudio) provided by Compuware. The DriverWorks tool can be used to generate a PCI bus driver framework, and then implement input and output processing in WDM, which can be achieved using the KIoRange class.

In the process of generating the driver framework, we can declare the resources to be used in the driver through the wizard; by calling the Initialize() function of the KIoRange class, we can initialize the resources (map the PCI local space); the application layer sends commands to the driver through the DeviceIoControl function to call the member function of KIoRange to implement the application layer's processing of the I/O space. Developing a windows driver for a PCI motherboard is to enable the PC to normally identify the card and allocate the required system resources.

2 Implementation of FFT algorithm

The system needs to develop and implement a program for collecting analog signals and performing FFT (Fast Fourier Transform) algorithm processing on the data for the DSP data acquisition module.

As a general case, assume that x(n) and X(k) are both complex numbers, because from the actual calculation process, there is no difference between real numbers and complex numbers. The only difference is that the imaginary part of a real number is zero and the expression is simpler. All calculations in the operation process are performed on real numbers. If the signal or spectrum is a complex number, the final calculation result is combined into a complex component. The basic unit of FFT operation is the "butterfly unit", and the basic form of the butterfly operation is shown in the following formula:

The operations of all butterfly units can be uniformly expressed as

(1)

(2)

Formula (1) can be expressed in terms of imaginary and real parts. The characters with subscript R represent the real part, and those with subscript I represent the imaginary part, that is,

(3)

According to the algorithm principle and the above description, a time-sampling FFT algorithm program is compiled in C language. The structure is divided into several parts: first, the code bits are inverted, then the number of butterfly operations is determined according to the number of calculated points, and then the butterfly operations are performed step by step to complete the FFT operation.

3 Design of application control software

Figure 6 Control software functional module block diagram

The functional module block diagram of the entire application control software is shown in Figure 6.

Based on the above control function module diagram, VC++ is selected to realize the human-machine interface of the system application software and the control function of the system. The development environment of VC++ integrates multiple functions such as editing, compiling, connecting, debugging, and wizards, and provides the MFC (Microsoft Application Foundation Classes) class library, which has become the industry standard.

The PC-side control software of the virtual instrument system we developed can realize data waveform display, port configuration, memory reading and writing, and instrument control functions. Its main interface is shown in Figure 7.

Figure 7 Main interface of the program

Conclusion

This design implements a data acquisition processing card based on DSP technology and PCI bus, and develops a virtual real-time multi-channel FFT spectrum analyzer application and host monitoring interface. By integrating DSP on the data acquisition card, the card can not only collect external signals in real time without dropping points, but also realize digital filtering and FFT spectrum analysis on the card.

After comprehensive debugging and rigorous testing, the entire system has met the design requirements and has been put into practical use.