Application of Microcontrollers with Hardware Vector Floating Point Units in Medical Electronics

Abstract: NXP microcontrollers are ideal for embedded applications that require high performance and low power consumption. The LPC3000 series ARM9 microcontrollers have an on-chip vector floating-point unit, which gives them a performance advantage in applications that require more algorithmic processing, especially single-precision and double-precision floating-point operations. The application of this product in the field of medical electronics is used as an example, and benchmark data based on NXP microcontrollers is provided. These data are collected using tools developed by the Embedded Microprocessor Evaluation Benchmark Consortium (EEMBC), which results in a standard methodology for measuring processor performance and energy consumption.
Keywords: microcontroller; ARM9; floating-point operation; medical electronics

Nowadays, more and more embedded control applications require signal processing, such as filtering, interpolation, noise reduction, spectrum analysis, demodulation, etc. Medical electronic equipment is an application field that requires signal processing. For example, image processing for ultrasound diagnosis requires a lot of digital signal processing when performing image reconstruction, edge processing, enhancement, image recognition and shape recognition. The control platform used for monitoring fetal heart rate, blood pressure and heartbeat, its computing module will also process the sampled raw data through a certain algorithm, and then feedback the processing and analysis results to the user through LCD and other means.
8-bit/16-bit microcontrollers usually consume a lot of computing resources to do these tasks. Today, powerful microcontrollers with built-in floating-point operations are beginning to appear, and 32-bit microcontrollers have enough power to implement many of these functions.

Evaluating the Performance of Microcontrollers
Compared with specialized DSP processors, microcontrollers have the following advantages for signal processing:
(1) efficient loop control; (2) rich peripherals; (3) single processor architecture, instruction set, and development tool chain; (4) unified interrupt and task switching environment, homogeneous memory; (5) the same operating system manages both control and signal processing tasks, based on MMU; (6) time to market is shorter due to greatly simplified development process; (7) popular microcontrollers are easily available, and development tools are low cost.
How to evaluate whether the performance of a microcontroller meets the application requirements is an issue that engineers need to consider in the early stages of project design. Evaluating and summarizing information from data sheets is an effective method, and another method is to use a certain type of evaluation board to perform specific performance tests and power consumption tests. Both methods have their own disadvantages.
Relying on comparisons based on data sheets is risky, and testing multiple hardware is usually impractical, time-consuming, and expensive. This article examines an intermediate solution using industry-standard benchmark data to evaluate performance and power consumption in the early stages of product design, after key components have been selected.
The goal was to investigate the system performance of NXP microcontrollers under several different test criteria and to correlate the collected data with energy consumption. This required measuring both performance and power consumption, which allowed for the measurement of overall energy consumption under a specific load.
During the evaluation, a three-step process was used: (1) abstracting the system characteristics by running various system test benchmarks and varying different system parameters; (2) interpreting the collected characterization data to establish the system's behavior; and (3) using the system's behavior to determine how to set control parameters so that the system performs as desired.

Characterization
In theory, performance testing is a qualitative or quantitative assessment of the behavior of a system. In practice, the behavior of the system may not be detailed enough to define a complete set of quality tests, and creating the tests may be too expensive to warrant their development. A good compromise for characterizing a system is to use a test bench as a test or series of tests executed in software that provide quantitative data that can be used to compare the behavior of different systems.
To characterize the microcontroller, a set of performance test benchmarks was selected from the EEMBC Auto-Bench group. These benchmarks help predict the performance of microcontrollers in automotive electronics, industrial, and general applications. Each benchmark is run through multiple iterations to eliminate the effect of some startup code that is only run once at the beginning of each test. One advantage of using this industry-standard benchmark suite is that the resulting data can be compared with test data from other microcontrollers of similar architecture to judge overall system performance.
The microcontroller tested here is based on the ARM926EJ-S core with a hardware vector floating-point coprocessor and a 32 KB instruction cache (I-cache). The test measures the performance of the floating-point coprocessor and the instruction cache. The Auto-Bench test benchmarks were run at different operating frequencies of the microcontroller, and the energy consumed during each benchmark execution was measured using Energy-Bench. Energy-Bench is another EEMBC tool that measures the energy consumed by the processor while the benchmark workload is running. The data collected from Energy-Bench provides an insight into the energy efficiency of the microcontroller under various different loads. Having chosen these tools to evaluate the microcontroller, the next step is to determine the performance of the microcontroller under different operating conditions.

Performance Analysis
To analyze the performance of a microcontroller, it is necessary to determine the overall system response under different conditions. In the test project, the performance of the floating-point coprocessor and instruction cache on the NXP microcontroller needs to be evaluated.
The Auto-bench benchmark suite was run, varying four parameters: operating frequency, CPU core voltage, instruction cache status, and floating-point coprocessor status.
Figure 1 shows a schematic diagram of the Auto-Bench/Energy-Bench test environment. It consists of three parts: data acquisition system (DAC), software development environment, and test target. The National Instruments DAC is connected to a PC running Energy-Bench, a power and energy consumption test software. The software test environment uses the Keil ^TM integrated development tool to compile, download, and run the Auto-Bench test benchmark. By isolating the three power supply voltages supplied to the microprocessor, Energy-Bench can measure the energy consumed in the Auto-Bench benchmark test and calculate the total energy consumed in each test.

Auto-Bench was run at four different frequencies (13 MHz, 52 MHz, 104 MHz, and 208 MHz) and with other test conditions combined, including turning the floating point coprocessor on or off and the instruction cache on or off. The floating point coprocessor was disabled by default, causing the compiler to use software floating point for any situation that required floating point operations.
There is much more data collected than can be presented in this article, but two representative cases are presented here to show how the collected characterization data determines the performance of the system. Figure 2 shows the results of the EEMBC finite impulse response filter (FIR) test data in a graphical manner. Figure 3 shows the results of the basic integer floating point data collected by EEMBC. The two different benchmarks were run at 13 MHz, varying the CPU core voltage between 0.9 V and 1.2 V. When the benchmark was run with the CPU clock set to 208 MHz, the AHB clock was set to its limit of 104 MHz. At all other test frequencies, the CPU clock and AHB clock were the same.

Figure 2 EEMBC’s finite impulse response (FIR) test data results

Figure 3. Basic integer floating point data results collected from EEMBC

The FIR benchmark was chosen as a test baseline because it does not contain floating point operations and provides useful data when compared to the basic integer floating point benchmark. Data from both benchmarks are provided to determine the necessary information needed to determine the performance of the instruction cache and the floating point coprocessor.
First, looking at the performance of the instruction cache, observe Figure 2 and the graph plotted against cycles/s. The data shows that at all frequencies, the absolute performance of the microcontroller is better when the instruction cache is enabled. Second, even though the instruction cache provides better absolute performance as the CPU clock frequency increases, the relative magnitude of the improvement is not linear. The reader can verify this behavior by observing the graph plotted against cycles/s/MHz. Figure 2 shows that the performance increases linearly by approximately 100 cycles/s/MHz for almost all CPU clock frequencies, except when running at 208 MHz, where the performance drops to 60 or 80 cycles/s/MHz depending on whether the instruction cache is enabled or not.
Clearly, the system runs faster when the instruction cache is enabled because fewer reads and writes to the AHB RAM are performed when the CPU is executing instructions from the instruction cache.
The non-linear performance characteristics are a result of the AHB clock having an upper limit of 104 MHz. When the AHB clock is slower than the CPU clock, the CPU must wait longer to fetch instructions from the RAM on the AHB bus, resulting in a smaller relative performance increase per MHz.
Next, we analyze the impact of the instruction cache on energy consumption. If we only consider the absolute power consumption of the power (Power) in Figure 2, we may conclude that turning off the instruction cache can save energy for the entire system. However, the Energy-Bench data shows that when the instruction cache is enabled, the energy consumed per benchmark cycle is actually lower than when the instruction cache is turned off. A
more detailed observation of the energy (Energy) graph shows that when the instruction cache is enabled, the energy consumed per cycle at 208 MHz, 1.2 V is even lower than other operating frequencies. In fact, there is a 10% to 12% improvement. In other words, when executing the same benchmark with the instruction cache enabled, running at high speed (208 MHz) for a shorter period of time has better energy efficiency than running at low speed (52 MHz or 104 MHz) for a longer period of time. From
Figure 3 and the graph of cycles/s, we can see the operating efficiency and energy consumption of using the floating-point coprocessor. This graph shows quite vividly the performance effect of the integrated floating-point coprocessor. At 208 MHz, with the instruction cache enabled and using software floating-point operations, the microcontroller runs at approximately 8,500 operations/s; with the floating-point coprocessor, this value jumps to over 32,500 operations/s, a performance improvement of over 280%.
The energy effect of the floating-point coprocessor can be examined in the energy graph in Figure 3. The energy per benchmark load at 208 MHz shows that the microcontroller consumes approximately 16 J per cycle when the instruction cache is enabled and using software floating-point operations; with the floating-point coprocessor, this value is less than 4 J/cycle - a saving of over 75% for the same workload.
Figure 2 and the cycles/s graph show that the performance benchmark data is equivalent at 13 MHz and supply voltages of 0.9 V and 1.2 V.
However, the power graph shows that the power consumption at 1.2 V is about 75% higher than that at 0.9 V.

System Control Parameters
In the test example, the EEMBC characterization tool was used to determine the performance of the instruction cache and floating-point coprocessor in the target test system. Based on this performance, general configuration parameters can be selected to provide the best conditions for system performance with low power consumption.
The following are some parameter selections that can control system power utilization and performance in environments similar to those of the EEMBC Auto-Bench benchmark suite:
(1) Enabling the instruction cache can provide better performance;
(2) Using the hardware floating-point coprocessor can significantly improve performance and reduce power consumption compared to software floating-point operations;
(3) At 208 MHz, the power consumption is better with the instruction cache enabled than at lower frequencies;
(4) For 13 MHz low-power operation, the core voltage is much better at 0.9 V than at 1.2 V.

Beyond these general outlines, the fact that the system performance is determined based on data from industry-standard performance and energy benchmarks is more important. These benchmarks are publicly available and can be independently verified.
Using the EEMBC Auto-Bench and Energy-Bench benchmarks, a consistent performance analysis can be easily demonstrated to others. Moreover, it can be repeated and verified.
Designing embedded systems is often a challenging task. Almost every embedded system has a relatively unique hardware configuration. It is often necessary to rewrite specific code for a specific embedded operating system. There are often very strict energy consumption constraints. This article provides a quantitative scientific test method to help embedded engineers consider how to choose a controller suitable for a specific application to build a system. Even if the embedded systems tested vary greatly, hard data can still help system evaluators compare the same performance characteristics. In this test
setup, the EEMBC characterization tool was used to determine the performance of the NXP microcontroller. This performance information was then used to select the best control parameters for the specific operating environment. The test routine quantified the system performance using the instruction cache and floating-point coprocessor of the microcontroller in the evaluation system. The collected characteristic data facilitates the definition of system behavior and provides a methodology to select operating parameters to control system performance and energy consumption.
Test results show that the use of hardware vector floating-point arithmetic units can improve system performance by about 5 times, reduce the amount of code, and reduce power consumption. The
hardware floating-point coprocessor VFP9 is a feature of NXP's LPC3000 series based on the ARM926EJ-S core. NXP's low-power 90 nm process technology can achieve this function with a very small chip area and extremely low power consumption, making the LPC3000 ARM9 microcontroller very suitable for medical electronics and other industry applications that require signal processing.