Design and Implementation of Multi-channel Digital Receiver

Abstract: In order to solve the shortcomings of low phase resolution of traditional analog intermediate frequency receivers, an intermediate frequency digital receiver technology based on software radio is proposed. According to the characteristics of radar signals, a design method of pulse width matching filter is proposed. A five-channel intermediate frequency digital receiver is designed by using orthogonal transformation theory based on polyphase filtering and digital filter method based on pulse width matching. The receiver uses five high-speed A/D converters to sample the input analog signals, and then sends the sampled data to FPGA for processing, and finally completes the extraction of the phase difference between each two signals. The experimental results show that the system has the characteristics of low cost, high accuracy, simple structure, and certain engineering application value.
Keywords: intermediate frequency digital receiver; orthogonal transformation; pulse width matching filter; FPGA

With the development of software radio, intermediate frequency digital receiver has attracted more and more attention as a key link in electronic reconnaissance system.
This design is mainly to develop an intermediate frequency digital receiver based on fixed intermediate frequency digital down conversion. This design demonstrates its feasibility through a simple introduction to the hardware and software of the five-channel intermediate frequency digital receiver, and a simple analysis of the experimental results is made.
The software part of this design is all completed in one FPGA, which improves the running speed of the system.

1 Hardware Design
The system block diagram of the five-channel digital receiver is shown in Figure 1. It consists of five conditioning circuits, five A/D converters, clocks, FPGAs, and peripheral circuits. After the intermediate frequency signal passes through the signal conditioning circuit, the differential signal is sampled by the A/D converter and sent to the FPGA for processing, and the extracted I and Q signals are sent to the direction finding processor for processing. The center frequency of the signal is 150 MHz and the sampling frequency is 200 MHz.

1.1 Transformer selection
Since the A/D converter requires differential input, this design uses two transformers in cascade to achieve differential conversion of analog signals. The connection method is shown in Figure 2. This cascade method can increase the coupling coefficient and stabilize the phase. The transformer in this design is the ADT1-1WT transformer from Mini-Circuits.

1.2 Selection of A/D converter
The center frequency f0 of the signal in this design is 150 MHz, and the bandwidth B is 10 MHz. According to the bandpass sampling theorem: suppose a frequency-band-limited signal x(t) is limited to (fL, fR). If its sampling frequency satisfies In

the above formula, n is the largest integer that satisfies fs≥2(fR-fL)=2B, then the signal sampling value x(nTs) obtained by sampling at equal intervals with fs can accurately determine the original signal x(t). The center frequency f0 and bandwidth B of the bandpass signal can also be expressed as:

In the above formula , n is a positive integer that satisfies fs≥2B. The sampling frequency selected in this design is 200 MHz.
The A/D converter in this design uses AD9230BCPZ-250 from ADI. The operating frequency can reach up to 250 MHz. The AD9230 sampled output data is 12 bits with high precision. In addition, it integrates a high-performance sample-and-hold amplifier and voltage reference on the chip, with a maximum analog differential input bandwidth of 700 MHz. This chip has a dual-ended input and is more suitable for sampling and quantizing differential signals.
1.3 Selection of clock chip
Since the sampling frequency of this design is relatively high (200 MHz), in order to ensure the best performance of the A/D converter, a high-precision, low-jitter clock signal is required. This design uses AD95163 as the system clock. AD9516 is a clock synthesis chip. The VCO integrated on the chip generates a frequency range of 1.75 to 2.25 GHz. Its output can provide three clock levels: CMOS, LVPecl, and LVDS, and it has 14-channel clock outputs. The clock frequency of its output can be changed by configuring the internal register to meet the requirements of different designs.

After determining the reference clock frequency, output frequency, and voltage-controlled oscillator frequency, the peripheral circuit design of AD9516 is designed using the ADIsimCLK software provided by ADI. The main external connection diagram is shown in Figure 3.

1.4 FPGA
Using FPGA to design sequential logic circuits has the advantages of fast speed, high precision, flexible design, high integration, and stable and reliable performance. This design uses ALTERA's Strat-ixⅡ series device EP2S60F1020, and the configuration chip is EPCI6. ALTERA's EP2S60 series FPGA has multiple dedicated power supplies, and the power consumption is a combination of multiple logic consumption. It has 48,352 logic units, 12 PLL phase-locked loops, 14 DSP blocks, and 112 embedded multipliers.

2 Software Design
The software implementation part of this design is all carried out in FPGA. The flowchart of software design is shown in Figure 4.

2.1 Digital Down-Conversion Based on Polyphase Filtering

That is to say, the two sequences x'BI and x'BQ are the 2-fold decimation sequences of the in-phase component xBI(n) and the orthogonal component xBQ(n), respectively. The time difference between xBI(n) and XBQ(n) is half a sampling point, which is caused by the use of odd-even decimation. Two delay filters can be used to correct it. The frequency responses of the two filters meet the following requirements:

In this design, according to the theory of digital down-conversion based on multiphase filtering, in the mixing stage, the in-phase component carrier is [10-10] and the orthogonal component carrier is [010-1], which saves the NCO design and multiplication operation, and is relatively convenient to implement.
2.2 Pulse width matching filter
2.2.1 Theoretical basis

It can be regarded as the cosine signal Acos(2πft) plus the window w(t), then its Fourier transform is the convolution of the two signal spectra, and its bandwidth should be determined by the main lobe width of the rear window function, and the main lobe width of X(f) is the same as the main lobe width of the rectangular pulse, which is 2/T.
The signal with pulse width of 0.1 μs, center frequency of 150 MHz and sampling frequency of 200 MHz is simulated. The simulation results are shown in Figure 5.

It can be found from Figure 5 that the spectrum of a single pulse signal contains an infinite number of frequencies. If a single pulse is to pass through the filter circuit without distortion, the bandwidth of the filter is required to be infinite. This is not feasible in practice. Since the energy is mainly concentrated in the main lobe, selective filtering can be performed as needed. In practical applications, if the rising edge information of the pulse is not required, the inverse of the pulse width can be selected as the bandwidth of the filter.
In actual situations, since the processing is for a single pulse signal, it is necessary to analyze different pulse width conditions. For narrow pulses, a relatively large bandwidth can be designed, while for wide pulses, a relatively small bandwidth can be selected.
In the case of a large range of signal pulse width variations, if a unified filter bandwidth is used to process the signal, more out-of-band noise will enter the receiver when the signal bandwidth is narrow, affecting the signal-to-noise ratio of the system, resulting in reduced sensitivity of the system and reducing the dynamic range of the system. Therefore. For narrow pulses, a relatively large bandwidth can be designed, while for wide pulses, a relatively small bandwidth can be selected.
2.2.2 Matlab simulation results
Matlab was used to simulate the signal-to-noise ratio. A 150 MHz intermediate frequency signal with a signal-to-noise ratio of 10 dB was input. The signal was filtered using low-pass filters with different passband widths and different stopband attenuations. The output signal signal-to-noise ratio and signal-to-noise ratio gain were analyzed, and the results shown in Table 1 were obtained.

Through simulation, it can be seen that the narrower the bandwidth, the greater the stopband attenuation and the higher the signal-to-noise ratio gain. However, when the stopband attenuation is greater than 30 dB, the signal-to-noise ratio is not significantly improved. Since the narrower the filter bandwidth, the greater the reduction in signal energy, the filter bandwidth cannot be infinitely small.
2.2.3 Implementation method
The actual processing of this system has a signal pulse width range of 0.2 to 150 μs. According to the different signal pulse widths, the signals are divided into three categories, namely 0.2 to 1 μs, 1 to 10 μs, and 10 to 150 μs. According to the different pulse widths, three filters with different bandwidths are designed to filter the signal, namely 5 MHz, 1 MHz, and 0.1 MHz. The filter design principle is shown in Figure 6.

In order to reduce the FPGA resource occupancy rate, the filter is designed by using filter multiplexing. The pulse width selection signal SEL (2.0) is used to select the filters at each level, and finally the signals of different pulse width types are filtered. The extraction module is added between the stages to reduce the data rate, which is conducive to the design of digital filters. The outputs of each stage, Data1, Data2, and Data3, are sent to the data selection output module MUX, and the final data output Data_out is selected by SEL (2.0). The clocks of the filters at each level are uniformly managed by PLL.
The system power consumption can be reduced by controlling the filter using the enable signals EN1, EN2, and EN3. At the same time, the filter multiplexing method can greatly reduce the required hardware resources.
The filter is implemented by using the FDATool tool provided by Matlab to design the filter, export the filter coefficients, and then import them into the IP core provided by QuarutsII. The extraction multiples between the filter groups must ensure that the spectrum of the extracted signal is free of aliasing. The extraction module can be implemented using D flip-flops. The clock and enable signal of each flip-flop are consistent with the clock and enable signal of the next filter.

3 Experimental results
The I and Q signals output by the pulse width matching filter are passed through the CORDIC algorithm to obtain the phase of each signal, and then the phase difference between each signal is calculated to obtain the following experimental results.
The signal source is used to generate two intermediate frequency signals with different pulse widths, 150 MHz, and a phase difference of 0 degrees. The phase difference is extracted, and the results are processed using Matlab to calculate the mean and standard deviation of the phase difference between each two channels. The experimental results are shown in Tables 2, 3, and 4. Table 2 shows the experimental results of a 0.5μs pulse signal passing through a first-stage filter. Table 3 shows the experimental results of a 2μs pulse signal passing through the first and second-stage filters, and Table 4 shows the experimental results of a 20μs pulse signal passing through all three-stage filters.

From Tables 2, 3, and 4, it can be seen that this design can correctly give the angles between the signals, and the more filter levels the signal passes through, the smaller the standard deviation of the phase difference, indicating that the use of the pulse width matching filter improves the signal-to-noise ratio of the receiver output signal.

4 Conclusions
This paper mainly introduces the software and hardware implementation methods of the five-channel digital receiver. The entire design uses an FPGA as the processing core of the system, and the five analog signals are synchronously sampled and sent to the FPGA through the A/D chip. This system mainly adopts the orthogonal transformation theory based on multi-phase filtering, uses CORDIC and the IP core in the FPGA to build the software design module, and adds the design of the pulse width matching filter after the orthogonal transformation to improve the signal-to-noise ratio of the output signal. The experimental results show that the system has the performance of high precision and simple structure.