Ultra-low noise amplifier design based on infrastructure receiver

introduction

For amplifiers to be suitable for wireless infrastructure receivers, they must meet key requirements such as low noise, high linearity, and unconditional stability. To this end, Skyworks has developed a new series of low noise amplifiers (LNAs) using 0.5 micron enhanced pHEMT (E-pHEMT) technology. The SKY67101-396LF covering 0.7–1.0 GHz and the SKY67100-396LF covering 1.7–2.0 GHz are suitable for GSM, WCDMA, TDSCDMA, and LTE infrastructure receive loop applications. To reduce costs and save PCB space, these LNAs are packaged in 2x2 mm QFN packages, and the same routing can be used for different frequency bands.

1 Specifications

Noise figure (NF) performance is one of the key parameters of a receiver system because it describes the ability to receive low-level signals. The lower the noise figure, the better the receiver sensitivity. The third-order intermodulation intercept point (IP3) characterizes the ability of the amplifier to suppress intermodulation distortion when there are signals of similar frequency. Absolute stability refers to the ability of the amplifier to not oscillate under any input or output load conditions. Other specifications, including current consumption, return loss, and human body model electrostatic discharge (HBM ESD), are equally important and must be considered during the LNA design process.

In order to obtain the optimal performance at the lowest cost, some special design techniques need to be adopted. The target specifications of the low-band and high-band LNAs are shown in Table 1.

Table 1. LNA specifications at VDD = 5 V, temperature = 25°C

2 Technology and topology

The design uses 0.5 μm enhancement-mode pHEMT technology to achieve excellent RF performance, ultra-low noise and high linearity. This technology also simplifies the MMIC design because it only requires a positive voltage at the gate of the FET.

This allows the power supply to be directly connected to ground and no additional components are required to form a self-biasing structure. This also allows circuit simulation to be quite accurate.

The design adopts a cascode LNA topology with high bandwidth, high gain and high reverse isolation.

3 Design steps

This paper will describe the design of SKY67101-396LF 900 MHz LNA in detail. The design of SKY67100-396LF 1900 MHz is realized by frequency adjustment technique using the same approach. The measured and simulated results of low and high frequency bands are shown in the “Comparison of Simulation and Measured Results” section.

3.1 Bias Circuit

Figure 1 shows an actively regulated bias circuit that stabilizes the LNA's current consumption to approximately 55 mA over temperature, process, and supply voltage.

R1 is used to set the total bias current by setting the voltage at pin 4. Any fluctuations in the supply bias are stabilized by the active bias circuit. Pin 2 receives the stabilized gate voltage through the L1 inductor. These components are also used to match the input impedance and noise figure source impedance.

The difference between the measured and simulated supply current over temperature (-40 °C to +80 °C) is approximately 3 mA (see Figure 2).

3.2 Noise Figure (NF) and Input Matching

Noise figure and input return loss are the main factors in LNA design.

The first stage of the cascode design is designed to achieve the best noise figure, output impedance match, and P1dB at a target drain-source current (Ids). The buffer stage is designed to achieve the best IP3 performance, output match, and P1dB without compromising other performance specifications. The topology is stable at almost all impedances through source feedback (absolutely stable after adding the interstage network, output network, transmission line losses, and parasitic impedances of SMT components. See the "Linearity" and "Stability" sections). Figure 3 shows the gain and NFmin (minimum noise figure) trade-offs of the topology as the frequency varies.

Figure 4 shows the noise figure constant circle, source-level stability circle, and available gain circle for the cascode topology at 900 MHz within the source-stable region of the Smith chart.

Considering the parasitic effects of SMT components and transmission line losses, the source impedance point Zs = 64 + j44Ω is selected within the 0.4 dB noise circle and 18 dB gain circle as a trade-off point between noise, gain, and input return loss matching.

The input matching network is implemented by C1, C2, and L1. C1 and L1 are selected as high Q components to obtain the best noise figure. C1 also serves as a DC block. For information on simulated gain, input return loss, and noise figure, see the Comparison of Simulated and Measured Results section.

3.3 Linearity (OIP3) and P1 dB

The input and output terminal loads, both in-band and out-of-band, will directly affect the linearity of the amplifier. The input and output loads of the amplifier can be scanned using source and load pull techniques. Here, the load pull measurement is performed after the source match is completed.

Once the source is matched to impedance Zs = 64 + j44 Ω to obtain the desired NF, input return loss, and bias current gain, P1 dB and OIP3 will depend on the output matching and feedback network. The simulation model was used to estimate the OIP3 at 0.9 GHz for two tones separated by 5 MHz, each with an input power of PIN = -20 dBm. Figure 5 shows the load-pull impedance on a Smith chart, with the circle indicating the optimum OIP3 region at 0.9 GHz.

Figure 6 shows the OIP3 and output power contours at 0.9 GHz.

Final load-pull simulation and matching should be performed after connecting the input and output matching circuits as shown in Figure 1. After completing the source and load matching, the OIP3 and P1 dB simulation results are shown in Figure 7 and Figure 8, respectively.

3.4 Stability

Stability is one of the most important requirements for LNAs. Typical specifications call for absolutely stable operation up to 18 GHz. Each stage must also be designed to operate absolutely stable, including all external components and biases under all conditions. High-gain, low-noise devices tend to become very unstable in most cases over this frequency range. To stabilize the device while meeting these requirements, a number of stability design techniques must be employed.

To solve the stability problem at low operating frequencies, an inductor is usually used at the source.

Source feedback inductors for input and noise figure matching can also be used to achieve stability. A common technique is to use a series-parallel LR network.

The effect of this network is to act as a low impedance at low frequencies and a high impedance at high frequencies.

Another common technique is to connect a series-parallel CR network from the drain to ground. This network acts as a shunt resistor at high frequencies and a high impedance at low frequencies. A shunt resistor to ground helps stabilize the device.

Another method to improve stability is to use parallel feedback between the output and input of the device. However, this method will degrade the noise figure. Therefore, it is usually used in the second stage (buffer) design and not in the first stage design. This feedback also benefits IP3, return loss (RL) and gain adjustment.

The stabilization circuit is integrated into the cascode LNA. The final simulated stability and measured stability results of SKY67100 and SKY67101 are shown in Figures 16 and 17.

3.5 Electrostatic discharge factors

Electrostatic discharge (ESD) is the transfer of static electricity between objects or surfaces at different electrostatic potentials and is extremely destructive to semiconductor devices. ESD must be addressed in the early stages of product development. Designs use power clamps, diodes, and stacked diode ESD protection circuits to achieve a Class 1A (>250 V) HBM rating across all pin combinations.

Other parts in the design also use ESD protection circuits, but special care is required to ensure that small-signal, large-signal, and noise-figure performance are not degraded.

4 Wiring

The SKY67100/SKY67101 application test board layout is designed to achieve the lowest possible noise figure and best stability. The test board is a 10 mil thick Rogers 4350B substrate stacked on a 50 mil thick FR4 substrate. Rogers 4350B material was chosen for the RF circuit because it has a low dielectric constant (εr) and is not susceptible to temperature changes in dielectric constant, which can achieve the best noise performance. The relatively low-cost FR4 material is used to carry the remaining laminates and increase mechanical rigidity and thickness. The microstrip line width and spacing design can accept commonly used 0402 size surface mount components while maintaining a uniform 50 Ω. The copper thickness is 1.4 mil to reduce circuit losses and their cumulative effect on noise figure.

5 Component Selection

Figure 9 shows the test board schematic. The input components C1, C2, and L1 determine the input match and noise figure of the device. For the best noise figure, high Q components are recommended.

Components R2 and C4 form the feedback circuit of the device if gain adjustment is required.

Output matching is achieved by components L2 and C5.

L2 is also used in the bias circuit to decouple components C6, C7, and C8.

By fine-tuning the output matching, linearity can be optimized.

6 Comparison of simulation and measurement results

Figures 10 and 11 depict measured and simulated gain plots of the SKY67100-396LF (1.9 GHz) and SKY67101-396LF (0.9 GHz) over a wideband frequency range. The SKY67101 has a gain of 18.2 dB at 0.9 GHz and the SKY67100 has a gain of 17.67 dB at 1.9 GHz.

Figure 12 depicts the input and output return loss of the SKY67101 device.

Input and output return loss measured at 0.9 GHz are both above 20 dB

Figure 13 depicts the input and output return loss of the SKY67100 device.

The in-band OIP3 and P1dB performance are shown in Figures 14 and 15. The OIP3 measurements for the SKY67101 are taken at 900 +/- 5 MHz, while those for the SKY67100 are taken at 1950 +/- 5 MHz.

The measured and simulated NF performance comparisons of the SKY67101 and SKY67100 are shown in Figures 16 and 17. A correction factor of 0.05 dB was applied to the SKY67101 and 0.1 dB to the SKY67100 to account for the losses caused by the input connector and the evaluation board transmission line to the first matching element.

The measured and simulated stability performance of the SKY67101 and SKY67100 are depicted in Figures 18 and 19. Both devices exhibit unconditional stability over bandwidth range with B > 0 and Rollet stability coefficient K > 1.

7 Conclusion

This article presents the design of two low-noise, high-linearity amplifier products, SKY67100 and SKY67101. These LNAs are implemented using enhanced pHEMT devices in a common source and common gate topology and are suitable for receiver applications in various wireless infrastructure products. They all use small, low-cost 2x2 mm QFN packages and use a common pin and wiring design.