Design of Boundary Scan Controller Based on USB 2.0

Abstract: The system uses CY7C68013 and its configuration chip EEPROM to complete the function of the USB interface part, and uses ACT8990 to complete the boundary scan part. In order to complete some logical functions and encrypt some circuits designed for this controller, CPLD EPM3032A is used. Then, the software design scheme of the entire controller is given, and the firmware design of CY7C68013 and the method of using Windows DDK development kit to develop firmware loading driver and controller driver are discussed in detail. The debugging results show that the developed boundary scan controller functions normally and meets the design requirements. It has the advantages of plug-and-play, no external power supply, simple and reliable connection, etc.
Keywords: boundary scan; USB2.0; JTAG; WDM driver

0 Introduction
With the development of technologies such as very large scale integrated circuits (VLSI), surface mount devices (SMD), and multilayer printed circuit boards (MPCB), the physical accessibility of circuit nodes on the integrated baseband printed circuit board of the unified measurement and control system is gradually deteriorating, the testability of circuits and systems has dropped sharply, and conventional testing is facing challenges. The study of VLSI chip data shows that most VLSI chips have boundary scan structures. If boundary scan technology is applied to board-level testing, it will undoubtedly play a very important role in the accurate diagnosis of circuit board connection faults and device failures. The boundary scan test master control system is an indispensable hardware system for realizing this technology. In the more than ten years since JTAG (Joint Test Action Group) proposed this technology, boundary scan test technology has been applied in some ways and will have broad application prospects. This design proposes a design scheme and implementation circuit of a boundary scan test master control system based on the USB bus based on the analysis of the working mechanism of the boundary scan test controlled system. This scheme has the characteristics of simple structure, low cost and portability.

1 Boundary scan structure and basic principles
1.1 Basic principles of boundary scan technology
The main idea of ​​boundary scan technology is to add a boundary scan unit composed of a shift register between the chip pins and the internal logic circuit of the chip to realize the serial setting and reading of the chip pin status, so that the pins are controllable and observable. Since the shift register allows test data to be shifted, updated, and latched, it can be used not only to test a single chip, but also to test the interconnection of circuit boards. Figure 1 shows a schematic diagram of the boundary scan path. The boundary scan unit forms a scan channel between the test data input (TDI) and test data output (TDO) of the main IC. When the IC is in normal working state, the input and output signals pass freely through the boundary scan unit from the normal data input (NDI) to the normal data output (TDO). Figure 1 Schematic diagram of the boundary scan path

1.2 Boundary Scan Physical Structure
The basis of boundary scan test is the boundary scan test bus and the boundary scan structure designed in the device. The boundary scan test bus consists of five lines: TDI (test data input), TDO (test data output), TMS (test mode select), TCK (test clock), and TRST (test reset). It mainly completes the test vector input, test response vector output and test control functions. The boundary scan structure in the device is mainly composed of the TAP test access port, TAP controller and necessary registers. The TAP controller receives commands from the boundary scan test bus, controls the actions of the boundary scan unit, and realizes the setting, reading and isolation of the device pin status.
1.2.1 Registers
The JTAG boundary scan register should at least include the boundary scan register (DR), instruction register (IR) and bypass register.
(1) Boundary scan register. The boundary scan register is used to store test data and test response data. It consists of a serial shift stage and a parallel latch stage. The working mode of the boundary scan register is as follows: the test data loaded into TDI is serially shifted into the boundary scan register at the rising edge of TCK, and the original content of the register is serially shifted out to TDO at the falling edge of TCK. The data shifted into the shift register can be latched into the parallel output latch; the parallel latch corresponding to the output pin can be output in parallel to the pin of the device, and the shift register can capture the logic output of the device in parallel; the parallel latch corresponding to the input pin can be output in parallel to the internal logic of the device, and the shift register can capture the input pin information.
(2) Instruction register. The instruction register consists of a serial shift stage and a parallel latch stage, and its bit number is defined by the chip manufacturer. Commonly used instructions include EXTEST, BYPASS, SAMPL-E, INTEST, etc. The TAP controller selects the specified register to connect between TDI and TDO according to the instruction selected in the instruction register.
(3) Bypass register. The bypass register consists of a one-bit shift register. When it is selected, it is directly connected between TDI and TDO of the device to obtain the shortest scan path. The main functions of the bypass register are: a. When the integrated circuit IC does not need scan access to the data register, it is disconnected from the scan chain to shorten the scan path length of the boundary scan structure; b. During the test, the integrated circuit IC is disconnected from a certain working mode.

1.2.2 TAP controller
The TAP controller controls the operation of the entire boundary scan mechanism. Its core is the 16 working state transition mechanism. The state transition is implemented by TCK sampling the value of TMS.

2 Hardware Design
The controller hardware can be divided into two parts: one is the USB control chip, and the other is the JTAG master chip. The controller uses the USB control chip to implement the USB protocol to communicate with the PC. At the same time, by operating the JTAG master chip, the data output to the JTAG bus complies with the IEEE1149.1 standard, thereby achieving the purpose of controlling the JTAG bus by the PC. The controller hardware structure is shown in Figure 2.

The EZ-USBFX2 chip CY7C68013 produced by the company is a USB interface control chip. The CY7C68013 chip includes an enhanced 8051 processor, a serial port engine (SIE), a USB2.0 transceiver, 8.5kB on-chip RAM, 4kB FIFO memory and a general programmable interface (GPIF). Its GPIF can be connected to any ASIC or DSP, and it also supports all current general bus standards. The USB interface chip of this system not only serves as an intermediary for data transmission, but also completes the exchange of control information and the execution of the control process between the portable computer. Transmission mode: Among the four transmission modes defined by the USB protocol, batch transmission and isochronous transmission are faster. However, batch transmission has error checking, which can ensure the correctness of data transmission. In this solution, because of the high requirements for data accuracy, batch transmission is adopted. The method of downloading 8051 running code from the PC is adopted. In this way, system software modification and function upgrade are more flexible, and the external ROM is saved, making the circuit more concise and reliable.
TI's boundary scan chip ACT8990 specifically for series DSP is selected. The internal structure of ACT8990 is mainly composed of queue management module, host module, serial module, event manager, counter, command management and read-write bus.

3 Software Design
The software design of this controller includes: firmware program, driver and CPLD logic code and the code of CY7C68013 configuration chip EEPROM. The software part includes three parts: test vector generation and analysis module, boundary scan test operation module and USB data transmission driver. The test driver resides in the boundary scan controller as a lower computer program. The boundary scan test operation module and the test vector generation and analysis module as upper computer programs mainly include: test file analysis, test vector generation, upper and lower computer communication, response vector analysis and auxiliary function module.
3.1 Test file analysis
When the test software is running, it first detects whether the chip boundary scan description file in the file library is complete, and then loads the test file. When the test is executed, the network table file of the board under test (the standard file generated by Protel software when designing the circuit diagram) is loaded into the system, and the file is analyzed to generate the test board chip information file and the chip pin interconnection network node file. According to the order of the chips on the boundary scan link, the chip name and package form are listed in the test board chip information file. The network node file gives the network node list between the two chips and the two chip pin numbers corresponding to the nodes, and removes the TMS, TCK, TDI, and TDO nodes in the interconnection nodes according to the definition in the boundary scan description file. The two generated files are used by the test vector generation and response vector analysis modules. The boundary scan description file is defined by the IEEE1149.1 standard. For general testing, the analysis of this file mainly obtains the correspondence between the chip physical pin number and the boundary scan register position (the bit close to TDO in the boundary scan register is defined as bit 0), various boundary scan test instructions, descriptions of the instruction register and boundary scan register, and the input and output types of the chip pins.

3.2 Test vector generation
When performing boundary scan testing, the first thing to do is to check whether the boundary scan link connection and working status are normal; whether the chip on the boundary scan chain is correctly installed, that is, to perform integrity testing. Only after the integrity test is passed can further test content be allowed to be executed. The integrity test is completed by capturing the data loaded into the instruction register when the scan link chip passes the CAPTURE-IR state of the TMS state machine and reading the chip ID code in the flag register and comparing it with the correct code of the boundary scan description file. While reading the capture value of the instruction register, the next test instruction can be written through TDI to save test steps. Figure 3 shows the flowchart of the test software.

The interconnection test between circuit board chips is the main test content of boundary scan test technology. It is mainly used to detect whether the network connections on the test board are normal, whether there are fixed logic faults, open circuit faults, bridge short circuit faults and other special faults. According to the test needs, taking into account the requirements of test time and test accuracy, 5 different test vector generation algorithms are used in the software (respectively, improved counting sequence algorithm, counting compensation algorithm, shift algorithm, equal weight anti-misjudgment algorithm, minimum weight-maximum difference algorithm). According to the test requirements selected in the main interface, the chips that do not need to be tested on the scan chain are sent to the bypass instruction, and the tested chips are sent to the external test instruction. Based on this criterion, the interconnection test instruction code is generated and serially loaded into the instruction register of the link chip. The interconnection test vector needs to be generated according to the algorithm selected in the main interface and the chip interconnection network node file. In order to ensure that the generated test vector can be accurately loaded into the interconnection network node, the generated primary test code needs to be processed. The transformation idea is to fill the generated test data of the corresponding network node pin into its corresponding position in the boundary scan link according to the correspondence between the chip physical pin and the boundary scan unit, so as to form a test vector that can be loaded into the scan chain. The functional test of the device mainly includes functional testing of chips or circuit boards with boundary scan structures and cluster testing of devices without boundary scan structures. Its test data and test response data are defined according to the chip logic. For the cluster test chip, the boundary scan unit of the chip with boundary scan structure around it needs to be used as the virtual boundary scan unit of the cluster test chip to load and capture the test data. Therefore, the network node file cannot be automatically generated by searching the network table file, but needs to be defined by itself. Its format is the same as the file generated when performing the interconnection test. The method of reading the pre-defined test vector in the file and transforming it into a test vector that can be finally loaded on the link is also the same as the interconnection test. When performing other sampling tests and built-in self-test tests, only the test instructions need to be entered to analyze the test results, and no additional test data needs to be generated.
3.3 Test response analysis and fault diagnosis
The test response analysis and fault diagnosis module analyzes the test response data to determine whether the target circuit board has a fault, the fault location and the fault type, and sends the analysis results to the main interface for display. When performing fault analysis, the test response vector must first be processed to remove junk data, and then the valid response data is substituted into the fault diagnosis function for analysis. When performing integrity test fault diagnosis, the CAPTURE-IR value and IDCODE value corresponding to each chip in the response vector are analyzed using the definitions in the chip list information file and the boundary scan description file, and compared with the standard values ​​to give a fault judgment. When performing interconnection test fault diagnosis, the test data corresponding to the network pin in the network node file needs to be extracted from the response vector based on the correspondence between the chip physical pins and the boundary scan unit. Then, according to the analysis rules and the input test vector, the network numbers with fixed logic faults, open circuit faults, bridge short circuit faults and special faults and their corresponding interconnection chip pin numbers are analyzed, and the possible misjudgment or confusion network is analyzed. The device logic function fault diagnosis and cluster test fault diagnosis methods are basically the same as the interconnection test. It is also necessary to extract the response vector of the corresponding test pin from the entire test response vector and compare it with the standard test results to determine whether the device logic function is normal.

4 Test results
(1) Scan link test First, use the shift instruction command to send out the sample preload instruction (SAMPLE/PRELOAD), and then use the shift data command to scan a series of 1010...10 test vector sequences into the scan link, and scan them back to the main control computer for comparison to determine whether the scan link is intact;
(2) Obtain device identification. Use the shift instruction command to send the device identification code (IDCODE) instruction to two chips that support the boundary scan test function, or send the bypass instruction (BY-PASS) to one CPLD and the device identification code (IDCODE) instruction to the other chip, and then use the shift data command to scan the 32-bit device identification from the device identification register to obtain the device identification of the device under test;
(3) Interconnection test. First, the sample preload instruction (SAMPLE/PRELOAD) is sent out with the shift instruction command, and then the test vector for interconnection test is sent to chip 1 with the shift data command. Then, the external test instruction (EXTEST) is sent out with the shift instruction command, and then the test response is scanned back to the main control computer from chip 2 with the shift data command, and compared with the correct response to diagnose and locate the simulated four-way short circuit fault and open circuit fault. The above tests all obtained correct results. In addition, in the test of the scan link, the FIFO module is fully verified to support uninterrupted full-speed scanning.

5 Conclusion
The emergence of the boundary scan mechanism is a leap forward in the idea of ​​testing and testability design. It provides a complete and standardized VLSI circuit testability design method. It can not only provide standard and effective solutions to traditional test problems; it can also improve the testability of the system at all levels. With the development of boundary scan technology and its increasingly wide application, the development of boundary scan test system has high practical significance and market value. As the operating part of the boundary scan test system, the boundary scan test software needs to be reasonably designed to automate the test process, standardize the test objects, and make the diagnostic results accurate and reliable, so as to better play the advantages of boundary scan test technology and promote the promotion and application of boundary scan test technology.