Design of Delay Line in Switched Current Circuit

O Introduction

Switching current technology is a new analog signal sampling, holding and processing technology proposed in recent years. Compared with the mature switching capacitor technology, switching current technology does not require linear capacitors and high-performance operational amplifiers. The entire circuit is composed of MOS tubes, so it is compatible with standard digital CMOS processes and can use the same process as digital circuits and be integrated on the same chip. Therefore, some people call it analog technology of digital process. However, there are some non-ideal factors in the switching current circuit, such as clock feedthrough error and transmission error, which directly affect the performance of the circuit.

This paper analyzes the problems existing in the second-generation switch current storage unit in detail, proposes an improvement method, and designs a delay line circuit. This circuit can accurately sample the signal and delay any clock cycle. The error generated by the second-generation switch current storage unit is solved, and various discrete time system functions can be easily constructed using this circuit.

1 Analysis of the Second Generation Switched Current Memory Cell

In the second generation switch current storage unit, in the φ1(n-1) phase, S1 and S2 are closed, S3 is open, and the transistor M is connected in the form of a diode. The sum of the input current ii and the bias current I charges the gate-source capacitance C. As the charging proceeds, the gate voltage vgs reaches a level that enables M to maintain the entire input current, and the gate charging current is reduced to zero, reaching a steady state. At this time, the drain current of M is:

In the φ2(n) phase, S1 and S2 are open, and S3 is closed. At this time, the output current is:

The Z-domain transfer function is:

From the above, it can be seen that the transistor M acts as both an input storage tube and an output tube, and the output current i0 is obtained only during the φ2 phase.

2 Delay Lines

From the results, due to the existence of clock feedthrough error and transmission error, the output waveform of the second-generation switching current storage unit (hereinafter referred to as the basic storage unit) is seriously distorted, especially the circuit distortion after cascading is more serious and cannot be applied in practice. Therefore, a delay line circuit is designed.

The circuit principle is as follows: the circuit is an array of N+1 parallel memory cells, and is controlled by a clock sequence. In the φ0 phase of the clock, the memory cell M0 receives the input signal, and the cell M1 provides its output. Similarly, in the φ1 phase, the cell M1 receives the input signal, and the cell M2 provides its output. This process continues until the cell MN receives its input signal and the cell M0 provides its output signal, and then the cycle repeats. Obviously, each cell provides an output signal one cycle before its next input, that is, N cycles (NT) after its previous output phase. If N=1, the delay line is an inverting unit delay unit, or when the input signal is continuous, it is a sample-and-hold circuit. At this time, the delay line circuit is the same as the basic memory cell. Note that for the N-1 clock phases of the cycle, each memory cell neither receives nor provides a signal. At these moments, the drain voltage value on the storage transistor changes to force each bias current to match the current held in its associated storage transistor. The Z-domain transfer function is given as:

If the basic storage unit cascade is used to delay N cycles, 2N basic storage units are required to be cascaded, and the clock feedthrough error and transmission error of the circuit will become more and more serious as N increases, and finally the original signal will be submerged in the error signal. If the delay line circuit is to achieve a signal delay of N clock cycles, it needs to be composed of N+1 parallel storage units and N+1 timing sequences. Since this circuit structure does not require cascading, it will not make the clock feedthrough error and transmission error larger and larger like the cascade of basic storage units. However, the clock feedthrough error and transmission error still exist, and the following is a solution.

3 Improvement of clock feedthrough error and transmission error

3.1 Improvement of Clock Feedthrough Error

The S2I circuit can be used to improve the clock feedthrough error. Its working principle is: in the φ1a phase, the gate of Mf is connected to the reference voltage Vref. At this time, Mf provides a bias current Jo for Mc. The current stored in Mc is ic=I+ii. When φ1b jumps from a high level to a low level, due to factors such as the clock feedthrough effect, the current stored in the Mc unit contains a current error value. Assuming it is △ii, the current stored in Mc is ic=J+ii+△ii. During the φ1b phase, the fine storage tube Mf samples the error current. Since the input current still maintains the input state, the current stored in Mf is If=J+△ii. When φ1b jumps from a high level to a low level, considering that △ii<

3.2 Improvement of transmission error

The reason for transmission error is that when the circuit is cascaded, because the current signal is transmitted, in order to completely transmit the signal to the next level, the output impedance must be infinite, but this is impossible to achieve in practice, and the output impedance can only be increased as much as possible.

The output resistance is calculated as:

Compared with the second generation basic memory cell, the output resistance is increased by times. Combining the advantages of the S2I circuit and the adjusted common source and common gate structure circuit, an adjusted common source and common gate structure S2I memory cell is constructed.

The circuit is simulated using 0.5μm CMOS process and level 49 CMOS model. The simulation parameters are as follows:

All NMOS substrates are grounded, all PMOS substrates are connected to the power supply, and the width-to-length ratio of all switch tubes is 0.5 μm/0.5 μm. The input signal is a sine signal with an amplitude of 50 μA and a frequency of 200 kHz. The clock frequency is 5 MHz, Vref = 2.4 V, and VDD = 5 V. Table 1 gives the main transistor simulation parameters.

The original circuit is connected and simulated according to the delay line structure, with a delay of 3 clock cycles (equivalent to 6 basic storage units cascaded). The simulation results are shown in Figure 1.

4 Conclusion

The shortcomings of the second-generation switching current storage unit are analyzed in detail, and improvement methods are proposed. A delay line circuit that can delay any clock cycle is designed. The simulation results show that the circuit has extremely high accuracy, so that the circuit can be applied in practice. Its Z-domain transfer function is. In practical applications, the circuit can be used as a basic unit circuit of a discrete time system.

Since the switching current technology is compatible with standard digital CMOS process and the entire circuit is composed of MOS tubes, this technology will have broad development prospects in future digital-analog hybrid integrated circuits.