Engineering Power and MEMS Signal Chain Simulation Using LTspice

summary

This article provides designers with background and guidance for simulating an engineering power solution using LTspice®. Once the engineering power solution has been optimized, the complete MEMS signal chain can be studied using LTspice. Some sensors have digital outputs, while others include analog outputs. For sensors that include analog outputs, the entire signal chain can be simulated using LTspice along with op amps, analog-to-digital converters (ADCs), and even available MEMS frequency response models.

Fast, good and economical

There are several standards for sharing power and data on the same line, including IEEE 802.3bu for Power over Data Lines (PoDL) and IEEE 802.3af for Power over Ethernet (PoE) with dedicated power interface controllers. These defined standards provide controlled and safe power connections through detection, connection checking, classification, and on/off fault monitoring. Power levels range from a few watts to tens of watts when safely powered. In contrast to the standardized PoE/PoDL specifications that apply to a wide range of applications, the term "engineered power (EP)" refers to a customized data line power design, usually for a single application. For example, the Hiperface DSL specification1 couples power and data to the same line for motor control encoder applications. Engineering power can also be used in some modern sensor systems.

Common shared power and data interfaces are coded to reduce the signal DC content, thus simplifying system design when sending AC signal components. However, many digital output sensor interfaces (such as SPI and I2C) have not been coded, have variable signal DC content, and are not a natural choice for shared data and power design. Encoding SPI or I2C requires an additional microcontroller, which increases the cost and size of the solution, as shown in Figure 1. To avoid the hassle of coding and adding an additional microcontroller, designers must try to take the fastest, best and cheapest approach, which requires careful design and simulation of the engineering power circuit. The engineering power circuit consists of inductors, capacitors, and protection circuits, which together form a filter.

Figure 1. Potential engineering power solutions for MEMS sensors, with tradeoffs in sensor solution size and design complexity

Engineering power background

Power and data are distributed over a pair of wires through an inductor-capacitor network. High-frequency data is coupled to the data line through a series capacitor while protecting the communication transceiver from the DC bus voltage. Power at the master controller is connected to the data line through an inductor and then filtered using an inductor at the daughter sensor node at the far end of the cable.

The inductor-capacitor network will create a high-pass filter, so a coupling solution must be added to the data line where the DC data content is not desired. However, some interfaces are not coded at the physical layer to remove the DC content, for example, SPI. In this case, the system designer needs to consider the worst-case DC content scenario, where all bits sent in the data frame are logic high (100% DC content). The selected inductor will also have a specified self-resonant frequency (SRF), above which the inductance value decreases and the parasitic capacitance increases. In this way, the engineered power circuit will act as both a low-pass and high-pass filter (bandpass). Simulation-based modeling can greatly help system designers understand this limitation.

When porting SPI over long distances, cables and components can affect system clock and data synchronization. The maximum possible SPI clock is set based on system propagation delays, including cable propagation delays, as well as master and slave component propagation delays. Although not discussed further in this article, designers should be aware of this additional limitation, as described in the article “Enabling Reliable Wired Condition-Based Monitoring for Industry 4.0 – Part 2”.

Figure 2 shows a simplified engineering power circuit that can be used for filtering or droop voltage and droop time analysis. The communication bus voltage droops due to the inductance of the data line power network, as shown in Figure 3. Voltage droop analysis is important because bit errors can occur in the network when the voltage droop exceeds 99% of the peak voltage. The system can be designed to meet specific voltage droop and time droop specifications. For example, 1000BASE-T Ethernet assumes a 27% voltage droop within 500 ns, as shown in Figure 3.

Figure 2. Engineering power supply, simplified circuit for analysis

Figure 3. Voltage drop and fall time

Equations 1 to 6 provide the inductor and capacitor values ​​to obtain the target voltage drop and fall time. Assuming that the voltage change across the DC blocking capacitors is negligible during the voltage drop, the following expression is derived to find the voltage drop of the series LR circuit:

Based on the target droop, droop time, and resistance, this equation provides an expression for the inductance: 4

The damping ratio of a series RLC circuit is found by the following equation:

Assuming ζ = 1 for a critically damped system, this gives an expression for C:

Substituting the above expressions for C and L yields the cutoff frequency of the circuit's high-pass filter:

For a critically damped system:

Why use LTspice for engineering power supply simulation?

There are several compelling reasons to use LTspice for engineering power simulations, including:

Realistic inductor models, including device parasitics that allow simulations to more closely correlate with real-world performance. Thousands of inductor models are available in the LTspice library from many well-known manufacturers including Würth, Murata, Coilcraft, and Bourns.

LTspice models for ADI physical layer communications transceivers are available to support multiple interface standards (CAN, RS-485) and are not typically available from other semiconductor manufacturers.

The flexible LTspice waveform viewer can be used to perform quick numerical evaluation of data line power delivery designs.

With the enhanced capabilities of LTspice, simulating power-consuming devices such as LDO regulators and switching regulators is very fast compared to ordinary SPICE simulators, and users can view waveforms for most switching regulators in just a few minutes.

Ready-made LTspice demonstration circuits reduce schematic acquisition time.

There are over 1000 ADI power device models, over 200 op amp models and ADC models, as well as resistor, capacitor, transistor, and MOSFET models available for you to complete the rest of your design.

Droop Analysis Using LTspice

Figure 4 provides a simplified data line powering simulation circuit. The circuit uses the LTC2862 RS-485 transceiver LTspice macro model and a 1 mH inductor (Würth 74477830). The realistic inductor model in LTspice includes device parasitics that allow simulations to more closely correlate to real design performance. The DC blocking capacitor value is 10 µF. In general, using larger inductor and capacitor values ​​can degrade data rate performance on the communication network. The data rate for the simulation test case was 250 kHz, which is roughly equivalent to 100 meters of cable communication when porting clock synchronous SPI over an RS-485 interface2. The input voltage waveform used in the simulation corresponds to the worst-case DC component with a 16-bit word and all logic high bits. The simulation results are shown in Figure 5 and Figure 6. The input voltage waveform (VIN) matches the output of the remote powered device (no communication errors). Figure 6 shows a zoomed-in view of the bus voltage differential waveform (Voltage A to Voltage B) used for droop analysis. The remote sensor node voltage extracted from the L2 inductor provides the 5 V ± 1 mV power rail.

Figure 4. Engineering power supply LTspice simulation circuit using LTC2862 (RS-485) and 1 mH Würth inductor 74477830

Figure 5. Simulation results of RS-485 bus differential voltage V(A,B) and drop points X and Y

Figure 6. Drop analysis of points X and Y

VDROOP, VPEAK, and TDROOP were measured using the LTspice waveforms of Figures 5 and 6. The L and C values ​​were then calculated using Equation 2 and Equation 4. As shown in Table 1, the calculated L value is 1 mH to 3 mH, but this value may vary depending on where the waveform is measured. The measurement at point X is the most accurate, yielding a correct inductance value of approximately 1 mH. The high-pass filter frequency (Equation 6) is a function of the fall time and voltage, and for point X, the frequency of 1 bit (half a clock cycle) is approximately 250 kHz/32, matching the input waveform (V3) shown in Figure 5.

When running the simulation shown in Figure 4, it is worth noting that the C8 capacitor is recommended to reduce the voltage overshoot on the sensor (VPOUT on the power extraction node). After adding C8, the overshoot is a maximum of 47 mV and settles to within 1 mV of the desired 5 VDC in 1.6 ms. Simulating without the C8 capacitor results in an underdamped system with an overshoot of 600 mV and a permanent voltage ringing of 100 mV from the 5 VDC target.

The value of C is 0.4 μF to 1 μF, as shown in Table 1. The value of C is smaller than the 10 μF DC blocking capacitor value because the circuit includes additional series capacitance (1 μF, 100 μF) and may be overdamped, which contradicts the calculations in Equation 1 to Equation 6.

Table 1. Droop analysis: using VDROOP/VPEAK and TDROOP to determine circuit inductance and capacitance

Using LTspice to simulate more complex power supply circuits