A technical explanation of the flyback converter without a snubber

All PWM converters have parasitic elements that can cause ringing waveforms that must be properly suppressed. If this is not done, semiconductor components may fail and noise levels will be higher than required. This article will introduce the most commonly used RCD clamp circuits for the popular flyback converter, and their design formulas.

Without a snubber, the leakage inductance of the flyback transformer will ring with the stray capacitance in the circuit, producing a large amplitude high frequency waveform as shown in Figure 1.

Many application notes and designs do not address this issue, ignoring the ringing waveform and converter operation. There are two problems: First, there is excessive voltage at the FET drain, which can cause avalanche breakdown and ultimately device failure. Second, the ringing waveform will become radiated and conducted throughout the power supply, load, and electronic system, causing noise problems and even logic errors. The ringing frequency will also appear as a peak in the EMI spectrum in the form of radiated and conducted EMI.

In most designs, this is unacceptable and circuit components must be added to suppress the ringing (using an RC snubber), clamp the voltage (using an RCD clamp), or both. The design of these networks is a combination of measurement and analysis to ensure robust and reliable results.

Primary RCD Clamp for Flyback Converters

Figure 2 shows an RCD clamp circuit that can be used to limit the peak voltage at the drain of a FET when an RC snubber is not sufficient to effectively protect against switch overvoltages. Once the drain voltage exceeds the clamp capacitor voltage, the RCD clamp works by absorbing the leakage inductance current. Using a relatively large capacitor can keep the voltage constant for one switching cycle.

The resistor in the RCD clamp will always waste power. Even with a small load on the converter, the capacitor will charge up to the voltage reflected from the converter secondary, which is vf. As the load increases, more energy will flow into the capacitor and the voltage will rise even more, which is vx, which is above the ideal square wave flyback voltage. The waveform defines these voltages, as shown in Figure 2.

Design Step 1 - Measuring Leakage Inductance

It is important to measure the leakage inductance of the flyback transformer before designing the snubber. Do not just guess at the inductance value, but understand that the worst-case specifications of the magnetic component manufacturer are often not accurate enough for the design. In addition, leakage inductance is frequency dependent and must be measured at the appropriate frequency value.

Design Step 2 - Determine Peak Clamping Voltage

Now we must decide how much voltage the power MOSFET can tolerate and calculate the amount of power the clamp will dissipate at the clamp level. The power associated with the leakage inductance, L, and the current worst-case current Ip at turn-off can be expressed as:

Formula 1

The analysis of RCD snubbers appears in papers and numerous application notes. It is assumed that there is no stray capacitance to charge and all leakage energy is conducted to the snubber capacitor from the leakage inductance. The capacitor is assumed to be large enough that its logic value does not change significantly during one switching cycle.

Using these assumptions, the power dissipation of the RCD clamp can be expressed as the energy stored in the inductor as follows:

Formula 2

In other words, the higher we let the clamping voltage on the switch go, the lower the total power dissipation. But of course, we have to balance this against the total voltage appearing across the power FET, so we can't just reduce the power dissipation arbitrarily.

A typical design can be used for a voltage vx equal to 1/2 the flyback voltage. In this case, the power dissipation is equal to three times the energy stored in the leakage inductance, which is not an immediately visible result. However, this is a conservative estimate. It does not account for the lossy discharge of the inductor, nor does it account for stray capacitance. In practice, the clamping losses of this design will be less than expected due to these results.

High voltage off-line designs these are often limited to using a FET with a maximum voltage of 650 or 700V. The voltage Vx will hardly limit the maximum input voltage, maximum current and FET breakdown voltage set. Do not exceed the Vds specified for the FET, realizing that breakdown may vary with temperature. Some designers rely on the avalanche capability of the FET, allowing it to regularly exceed the breakdown voltage. This is not recommended for reliable power supply design.

Design Step 3 - Selecting the Clamping Resistor

The buffer capacitor needs to be large enough to maintain a relatively constant voltage while absorbing leakage energy. Apart from this consideration, its logic value is not critical and does not affect the peak voltage when the buffer is operating normally.

The resistor is a critical component in determining the peak voltage vx and therefore needs to be selected according to the following formula:

Formula 3

A large value resistor will slow down the discharge of the clamp capacitor, helping the voltage to rise to a higher value. A small value resistor will result in a lower clamp voltage, but power dissipation will increase.

Design Step 4 - Calculate Power Losses

Now the snubber design is complete, but we often need to know what the power dissipation is for the current in addition to the worst-case current Ip in the above formula. Use the following formula to calculate the voltage rise of a known snubber for a given peak current I and leakage inductance L.

vx is the voltage rise value, which is higher than the flyback voltage and can be expressed as:

Formula 4

The power consumption can be expressed as:

Formula 5

Design Step 5 - Experimental Verification

Experimental verification of the design is essential because there will be consequences not accounted for in the equations and your circuit will have non-ideal components. Figure 3 shows the effectiveness of a circuit to clamp the FET drain voltage peak.

Figure 3. Flyback converter drain voltage with primary RCD clamp.

This value also gives a limit for the RCD clamp. After the clamping period is over, the circuit resumes ringing. With ideal components, this will not happen. However, the diode of the RCD clamp has a finite reverse recovery time, which helps the leakage inductance current flow in the opposite direction of the diode, which can cause ringing. The choice of the type of diode for the RCD snubber is critical. It must be as fast as possible and have the appropriate voltage rating.

The severity of this ringing will depend on the voltage applied in reverse across the RCD diode. The higher you allow the clamping voltage to climb, the lower the power dissipation, and the higher the voltage and dv/dt applied across the diode, the greater the ringing will be.

The subsequent ringing can again be suppressed by using an RC snubber.

Summarize

RCD clamp circuits are very useful for all flyback converters to reduce stress on the power FETs. Make sure the clamp is designed to limit the voltage under the worst-case operating conditions (high voltage and maximum current limit) to below the rated voltage of the component. The design equations in this article take the guesswork out of the clamp design.