Research and design of high efficiency class F RF power amplifier

　　1 Introduction

　　RF power amplifiers are widely used in various wireless communication transmission equipment. With the rapid growth of mobile communication services, the requirements for low consumption, high efficiency and small size are also increasing rapidly. It is well known that RF power amplifier (PA) is one of the many design modules with the largest power loss in RF transmission. The current development of the third generation of communication has promoted the update of power amplifiers. As the core part of the communication base station, the efficiency of PA directly affects the efficiency of the entire base station. Therefore, studying and solving the efficiency problem of power amplifiers has become a hot topic in current research. The theoretical efficiency of Class F amplifiers can reach 100%, so Class F power amplifiers have good research prospects.

　　2 Study on the Principle of Ideal Class F Amplifier

　　Figure 1 shows the basic structure of a power amplifier, which includes a transistor, a DC source, an output matching network, and an input matching network. DC bias is used as a DC source. The transistor can be a FET or a BJT. This article uses FET as an example. The drain of the transistor is connected to a DC bias voltage Vd through an RF choke and matched to an optimal load of 50 Ohms through the output network.

　　Figure 1 Basic structure of a power amplifier

　　The Class F amplifier achieves a common improvement in efficiency and output power by using a harmonic oscillator circuit in the output matching network, resulting in a short circuit for even harmonics and an open circuit for odd harmonics at the drain load. The drain voltage is composed of odd harmonics and is close to a square waveform. The drain current contains the fundamental and even harmonics, approximating a half-sine wave. Because there is no overlap between the drain voltage and current, the ideal efficiency can reach 100%.

　　The impedance condition for 100% ideal drain efficiency at the device drain is:

　　To realize the working voltage and current waveform signals of the Class F amplifier, odd harmonics can be used to approximate square waves, and even harmonics can be used to approximate half-sine current waveforms. The expressions are as follows:

　　in,

　　The midpoints where the voltage waveform reaches its maximum and minimum values ​​are at

and

The maximum flatness requirement at minimum voltage is

Even-order derivatives are 0.

,

When is an odd number, the odd-order derivative is equal to 0. The even-order derivative of the voltage waveform given by the above formula must be defined.

　　3 Theoretical Analysis and Design Methods

　　The ideal class F amplifier appears to contain infinite harmonics, but it is impractical in design. For example, the drain-source capacitance Cds will generate a large number of high-order harmonics short-circuited at microwave frequencies. Similarly, the parasitic capacitance and inductance of the drain-output make it almost impossible to generate even-order harmonic short-circuit and odd-order harmonic open-circuit. Usually, many harmonics entering the output network need to realize the impedance at each harmonic frequency, which will produce a very complicated circuit and more output loss, thus reducing efficiency. Therefore, only a small number of harmonics, such as 2nd and 3rd harmonics, are considered in many designs. They have a great effect on output energy and efficiency.

　　Raab studied the effect of output power performance and efficiency under limited harmonics. This helps designers consider the complexity and efficiency of the output network when designing. Table 1 shows the maximum efficiency of different harmonics. As we can see, the maximum efficiency of the class A amplifier is 50%. When there is only the fundamental frequency, the current and voltage m and n are both 1. The maximum efficiency increases from 50% to 70.7, 81.7, 86.6, and 90.5 for the 2nd, 3rd, 4th, and 5th harmonics respectively. mn represents the maximum harmonic order of the drain current and voltage.

　　Table 1. Maximum efficiency of Class F power amplifiers

　　When only the 2nd and 3rd harmonics are considered (3rd harmonic peaking), the maximum efficiency can reach 81.7%. The output network circuit including the 3rd harmonic peaking is shown in Figure 2a. A parallel resonator is added to the drain output at 3f0 to provide 2f0 short circuit and 3f0 open circuit. Another parallel resonator is connected in parallel with the load impedance to ensure the best load at f0. RL is the best drain load.

　　(2a) 3rd harmonic output network

　　(2b)

　　Figure 2 Harmonic output network

　　Figure 2b shows two other possible parallel resonator circuits and initial values ​​of the components for the connected resonator circuit construction. An equivalent microstrip impedance-peaking circuit and its initial principle values ​​are also given. It can provide short circuits for all even harmonics and open circuits for the third harmonic. However, the design of an actual Class F PA is much more complicated because of parasitic reactances, nonlinear drain current Ids and nonlinear Cgs, Cds. The equations given in Figure 3 can provide a good starting point for the design of a Class F amplifier.

　　4 Design Examples

　　In this paper, when designing a class F amplifier, the output harmonics are tuned. When the input network provides conjugate matching at the gate input, the output network provides an even harmonic short circuit and an odd harmonic open circuit. The output matching network enables the optimal load of the fundamental wave to be obtained at the drain output. In the equivalent microstrip impedance-peaking circuit in Figure 2b, only the second of the three electrical lengths needs to be additionally corrected according to the parasitic parameters of the transistor, and the remaining actual microstrip line sizes can be calculated based on the substrate parameters and frequency.

　　The design uses Cree's GaN HEMT, with a base frequency of 1.25GHz, a bandwidth of 100MHz, an input power of 28dBm, a substrate material Er=3.38, a board thickness of 0.4mm, and an input network designed under the same frequency class B working mode, with a gate voltage of VGS =-2.5V and a drain voltage of VDS=28V. The maximum PAE of the ADS simulation result is 84%, and the implementation circuit and test frame are shown in Figure 3.

　　Figure 3 Test circuit and test frame diagram

　　The maximum power added efficiency of the preliminary test results is 65.5%. By further adjusting the circuit and the input and output capacitors, the PAE is 70.32%. It is slightly lower than the simulation result, but a higher efficiency has been achieved. There are many reasons for the low efficiency. The improvement of the measurement device and the readjustment of the circuit may further effectively improve the efficiency of the circuit.

　　The actual measurement results of this design at the center frequency of 1.25GHz are shown in Figure 4. Compared with the current high-efficiency amplifiers at home and abroad, it achieves higher efficiency while ensuring output power, and has achieved good success in the implementation circuit of the Class F amplifier.

　　Figure 4 Output power and PAE relative to input power

　　6 Conclusion

　　This paper studies the theory of class F power amplifiers, analyzes its circuit working principle and experimental design methods. And through the design and experiment of a new type of class F amplifier, it is confirmed that it is possible to achieve high efficiency and high power operation. In actual tests, a power added efficiency of 65.5% has been achieved without adjustment. Since there is no accurate basis for the factors affecting efficiency during the adjustment process, the adjustment process is difficult. Finally, a PAE greater than 70% was achieved and the output power reached 10W.