Designing external power supply solutions with energy-saving concepts

　　1. Promote or redesign with energy-saving concepts

　　High efficiency of the power supply at light load is the key factor. The efficiency of the working mode is the average of the efficiency when the power supply works at 25%, 50%, 75% and 100% load: continuous high efficiency over the entire load range is more important than high efficiency at heavy load; the most ideal control scheme is to reduce the frequency accordingly as the load decreases.

　　In order to provide higher energy efficiency for power supply systems, many standards have been issued internationally, such as the International Energy Agency's "1W Plan", the new version of the US Energy Star, and the US 80 PLUS. So what are the new EPS energy efficiency standards?

　　New external power supply (EPS) energy efficiency standard: Applicable to all single-channel external power supplies (EPS) with power ranging from less than 1W to 250W; Equivalent to Energy Star (EPA) standard (CEC, CECP, AGO, EU; Applicable to both AC-DC and AC-AC adapters and chargers; Other states in the United States will also use this standard/regulation in progress; China CECP standard will take effect from January 1, 2005; In Australia, it will take effect from April 1, 2006; The EU will also adopt the corresponding provisions in the working mode in the standard from January 1, 2007.

　　With the introduction of these new standards, new challenges have been posed to power supply design. To this end, new initiatives are needed to face new challenges. The first is to use energy-saving concepts to promote or redesign. That is, energy saving has become an important design requirement; 60% of existing solutions today cannot meet the requirements of the new standards; energy-saving standards for external power supplies (EPS) have been promulgated; many companies have launched new product series that can make your design meet all current and proposed standards. In addition, new technologies must be used to meet design challenges. For example, in order to reduce energy consumption in standby mode, ON Semiconductor focuses on other technologies, such as skip cycle standby mode, PWM controller master PFC (turn off PFC when light load to reduce standby energy consumption). In addition, integrating many new technologies and functions into the chip, such as DDS (dynamic self-powered), frequency jitter, Soxy-less (no coil demagnetization detection), etc., can simplify the design of peripheral circuits and reduce power loss accordingly. This paper only studies the two aspects of selecting energy-saving chips and using intelligent power management technology to save energy.

　　2. Selection of energy-saving chips

　　2.1 LinkSwitch-LP device features and working mode

　　LinkSwitch-LP series features: easy to design, few peripheral components; primary circuit controller limits output current when load exceeds peak power point - no current sense resistor required; complete fault protection - overheating, short circuit and open loop; can operate within universal input voltage range (85-265VAC); Figure 1 shows the non-simplified circuit (a) and output characteristics (b) of a typical application. The outstanding feature is energy-saving technology: no additional components are required, easily meeting all global energy-saving standards; no-load energy consumption at 265VAC input is <150mW; on/off control can have constant efficiency at extremely light loads - ideal for meeting mandatory CEC standards.

　　LinkSwitch-LP system cost advantage: As shown in Figure 1, frequency jitter reduces EMI and adopts simple EMI filtering; the inductor is used for both filtering and fuse function, see point A in Figure 1; the internal high-voltage constant current source eliminates the startup and bias circuits, see point B in Figure 1; the internal current detection circuit eliminates the external current detection resistor, see point C in Figure 1; strict device parameter tolerance, low current limit point, allowing the primary winding to not use the box position circuit, see point D in Figure 1; low-cost transformer feedback voltage regulation, see point E in Figure 1; the output voltage is determined by the voltage divider resistor, with accurate FB pin voltage, see point F in Figure 1; the on/off operation does not require frequency compensation components, see point G in Figure 1. It is optimized for applications with minimum cost requirements and loose constant voltage/constant current requirements.

　2.2 Typical Applications

　　Figure 2 shows a typical alternative solution for a 6V 330mA constant voltage/constant current (CV/CC) output power supply circuit using the LNK564 IC. Here we analyze the characteristics of the solution.

　* Input circuit

　　AC input differential mode filtering can be achieved by forming a very low-cost input filter with C1 and L1. The frequency jitter characteristic of LNK564 eliminates the input pi (C, L, C) filter components, requiring only a large-capacity capacitor. Adding a bushing also allows the input inductor L1 to be used as both a fuse and a filter component. This simple Filterfuse input stage further reduces system cost. Another option is to use a fuse resistor RFl to provide the function of a fuse.

　　In some applications, if lower EMI margin and/or reduced input surge withstand capability are allowed, input diode D2 can be removed from the neutral line. In such applications, D1 needs to be a diode with a withstand voltage of 800V.

　　*About LNK564 on/off control

　　The design uses a simple bias winding (T1 pulse transformer/1.2) voltage feedback method, with LNK564 on/off control. When the switch is off, the resistor divider formed by R1 and R2 determines the output voltage on the bias winding of pulse transformer T1. In the constant voltage operating region on the V/I curve (see Figure 1(b)), the LNK564 device enables/disables switching cycles to maintain the voltage at the FB pin at 1.69V. Diode D3 and low-cost ceramic capacitor C3 provide rectification and filtering of the primary feedback winding (T1/3.4) voltage. When the load increases beyond the constant power threshold, the FB pin voltage begins to decrease as the power supply output voltage decreases. The internal oscillator frequency decreases linearly in this region until it reaches 50% of the startup frequency. When the FB pin voltage drops below the auto-restart threshold (usually 0.8V at the FB pin, which corresponds to a power supply output voltage between 1V and 1.5V), the power supply will shut down for 100ms and then restart for 100ms. It will continue in this mode until the FB pin exceeds the auto-restart threshold. This feature reduces the average output current in the event of an output short circuit.

　　In this solution, C3 can be increased to 0.47mF or higher to further reduce the no-load consumption.

　　Due to LNK56

　　The current limiting regulation technology used in 4 makes the current limiting point tolerance very accurate, and the newer transformer structure technology is used to achieve the design of no clamp circuit in the primary circuit. The peak drain voltage can be controlled below 550V at 265VAC input, which has a very large margin for 700V withstand voltage (BVDss) MOSFET tubes.

　　* Output circuit tube selection

　　The output is rectified and filtered by output rectifier D4 and filter capacitor C5. Due to the auto-restart feature, the average short-circuit output current is much lower than 1A, so the low-cost D4 rectifier can be used. The output circuit only needs to be able to handle the continuous short-circuit current when the power supply output is shorted. Diode D4 is an ultrafast recovery diode to optimize the output V/I characteristic. Optional resistor R3 acts as a dummy load to limit the output voltage when the output is no-load. Despite this dummy load, the no-load power consumption can still be maintained within the target range of about 140mW at 265VAC. By increasing the value of R3 to 2.2kW or higher, lower no-load power consumption requirements can be met while limiting the output voltage to less than 9V. If required, an optional Zener clamp diode (VR1) can be installed in the blank space on the left side of the circuit board to limit the maximum output voltage of the power supply in the open loop condition.

　　3. Save energy with intelligent power management technology

　　In recent years, power management technology has developed by leaps and bounds, and there are more and more design options to choose from. Government environmental groups and consumers continue to put pressure on electronic product manufacturers, urging them to increase product functions while also reducing system energy consumption. At present, the development of the portable electronic product market is particularly eye-catching. For example, wireless communication products are constantly being innovated and their functions are becoming more and more diverse, which is the hero driving the development of the entire market. According to the current development trend, mobile phones, personal digital assistants, MP3 players, digital cameras and portable electronic game consoles are all moving towards smaller size, higher speed and more complete functions. In order to ensure that the "talk time" (i.e. battery life) can be extended to a satisfactory level, engineers have been committed to improving the design of the power supply subsystem.

　　The battery life of portable electronic products depends on two key factors, one is the power conversion efficiency, and the other is the system's energy management method. The power conversion system is responsible for converting the battery supply voltage to the specified power supply mains voltage as efficiently as possible, while the energy management system provides power supply that just meets the needs of the actual application in real time to save energy.

　　3.1 Improving the efficiency of the voltage regulator is one of the effective ways to save energy. Using PowcrWis technology to reduce energy consumption

　　The new generation of energy-saving technology focuses on adjusting the frequency and voltage of the processor to reduce energy consumption.

　　For battery-powered systems, whether the system can stay on for a long time depends on its energy consumption. Simply reducing its frequency will only reduce the average power consumption: it will not reduce the energy required for a particular computing operation. The system voltage must be lowered to truly save energy. Dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) are two power management technologies that can reduce the system voltage.

　　What is adaptive voltage scaling? What are the benefits of this technology? Adaptive voltage scaling is performed by an embedded adaptive power controller (APC) that tracks performance changes in the system processor. The APC accurately communicates system processor performance (frequency), temperature and process changes to an external adaptive power management chip through a PowerWise high-speed low-power interface. The power management unit then automatically adjusts the supply voltage of the system processor based on performance requirements. Previous voltage scaling schemes were open loops. The CPU controls the voltage maintained in a frequency/voltage check table and provides voltage through a dedicated interface and power management circuits. The value in the check table is false and the value under the worst case. Adaptive voltage scaling mitigates CPU interference and reduces pressure in a closed loop approach. The adaptive power management provided by PowerWise technology combined with the accurate dynamic performance settings provided by ARM's Intelligent Energy Manager provides unprecedented ideal results.

　　The dynamic voltage scaling (DVS) technology first pairs different voltages and frequencies into different combinations, and then selects the most suitable voltage/frequency combination according to actual needs during adjustment. A variety of power management integrated circuits PMICs are available, including LP3906 and LP3907 that support DVS mode, and LP5550, P5551 and LP5552 that support both DVS and AVS modes. Dynamic voltage scaling (DVS) technology can save power and energy, and also reserve some extra space for the supply voltage to support systems with different technologies and temperatures. Although this reserved extra space is sufficient to cope with the most severe situation, it will waste more power in actual application. As long as we turn off the power supply loop of the system, the control loop can flexibly adjust the operating voltage and reduce it to the minimum to save energy as much as possible. PowcrWis technology uses this method to save energy.

　　3.2 PowerWise Features

　　The PowerWise interface (PW) can support intelligent energy management systems.

　　PowerWise is an energy management technology that targets the overall needs of the system, ensuring that battery-powered electronic products can utilize adaptive voltage scaling (AVS) technology and control the switching of different states. PowerWise technology uses a closed-loop AVS system with a high-speed serial power management bus to ensure that the processor can use the lowest voltage at any time and at any frequency to minimize dynamic energy consumption.

　　PowcrWise technology can also provide bias for the processor's potential well. Since the supply voltage Vdd has been lowered to reduce dynamic losses, the threshold voltage of the transistor must also be lowered to ensure that the drive voltage can be maintained at a high level, but the disadvantage is that leakage and static power loss will increase. As long as we provide a reverse bias for the potential well, the leakage will be reduced. In addition, taking the same supply voltage (Vdd) as an example, we also provide a forward bias for the potential well to increase the drive voltage.

　　The standard system configuration that can support the PowcrWise closed-loop AVS function must have the following basic components: an advanced power controller built into the processor, a power management integrated circuit with a PWI slave, and a two-wire PWI serial bus that connects the two. The power management integrated circuit is responsible for providing a different voltage to the processor, and the voltage is regulated by the PWI master controller in the advanced power controller. The master controller transmits the relevant commands to the PWI slave, and then the relevant circuits make adjustments.

　　The advanced power controller is responsible for receiving commands from the main processor, providing an operating environment for the voltage control process that is not affected by the processor, and tracking the operating speed of the logic circuit in real time. The advanced power controller is always on alert and constantly monitors all system parameters, such as system temperature, load, transient, process and other related changes. Whenever the advanced power controller receives news that the frequency is about to change, it will make a judgment in advance to determine how much power the system needs to operate stably at the new frequency. The entire process is monitored by a closed-loop circuit. For example, the advanced power controller first transmits the voltage regulation command to the PWI slave via the PWI interface, and then the servo device adjusts the voltage to an appropriate level.

　                       FIG3 is a schematic block diagram of a typical chip LP5552 that uses PowcrWise technology to reduce energy consumption. Its technical parameters are as follows.

　　The number of LP5552 outputs is 7. The output voltage and current are: 2 buck regulators with an output voltage of 0.8v to 1.235v and an output current of 800mA; 5 buck regulators with an output voltage of 0.8v to 3.3v and an output current of up to 250mA. The input voltage range is 2.7V to 4.8V. The interface is PWl 2.0. The package is micro SMD-3.

　　3.2 PowerWise Technology Application

　　PowerWise technology is an advanced energy management solution, mainly for current and future digital devices that are energy-constrained, suitable for dual-core processors, mobile phones, portable radios, personal digital assistants, battery-powered electronic products and portable devices. It can reduce the energy consumption of digital processors by 70%, thereby extending battery life, supporting more functions and improving user experience. PowerWise uses technologies such as adaptive voltage regulation (AVS) and threshold voltage regulation to automatically minimize the working and leakage power consumption of digital logic integrated circuits while maintaining minimal system overhead.

　　PowerWise technology provides an optimized closed loop between the single-chip system and supporting components without CPU intervention. Embedded PowerWise technology is processor-independent because it is synthesizable.

　　4. Conclusion - Power sequencing technology is also an ideal energy-saving solution

　　The energy-saving technology for different types of products is also different. The application of power sequencing technology is also an ideal solution. Because in many high-power systems, the cost of space and cooling systems is very high. Therefore, it is extremely important for any POL converter to be compact, efficient and have low quiescent current to meet the new "green" standards. In addition, many microprocessors and digital signal processors (DSPs) require a core power supply and an input/output (I/O) power supply, which must be sequenced at startup. Designers must consider the relative voltage and timing of the core and I/O voltage sources during power-on and power-off operations to meet the manufacturer's performance specifications. Without proper power sequencing, latch-up or excessive current consumption may occur, which may cause damage to the microprocessor I/O port, or damage to the I/O port of supporting devices such as memory, programmable logic device (PLD), field programmable gate array (FPGA), data converter, etc.