Capacitor solutions for piezoelectric failure

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High-voltage and high-capacitance capacitors are generally realized by electrolytic capacitors or film capacitors, which are generally large in size. Despite years of development, the miniaturization of high-voltage and high-capacitance capacitors is still very limited. The current progress is mainly in high-voltage, but it is difficult to take into account high capacity at the same time; or high capacity is achieved but the voltage is generally less than 50V.

In order to obtain both high withstand voltage and high capacity, the common practice in the industry is to stack multiple ceramic capacitors together according to the specifications of DSCC 87106/88011 and MIL-PRF-49470. This practice takes up a lot of space, is heavy, and is expensive. Therefore, there has always been a demand in the industry for lighter, smaller capacitors with high withstand voltage and high capacity.

Limitations of past technologies

Failure modes determine design limitations, and the existence of multiple failure modes also limits the capacitance increase of medium and high voltage capacitors. Some failure modes are external, such as fracture caused by mechanical or thermal stress, but at the same time we also need to explore internal failure modes, which are within the control of manufacturers.

The design constraints of multilayer ceramic capacitors have changed over time. The main limiting factors faced by early multilayer ceramic capacitors were point defects and impurities in the dielectric material itself, which affected the quality and purity of the material, as shown in Figure 1, thus limiting the upper limit of the number of layers inside the capacitor and the minimum thickness of each layer.

 

 

As the quality of the dielectric material itself improves and the operating procedures improve, the limiting factor becomes the strength of the dielectric material itself, and once this factor is resolved, we can expect to manufacture larger and thicker capacitors without worrying about dielectric breakdown or point failure, as shown in Figure 2.

 

 

However, a new failure mode has emerged, which we call piezoelectric stress fracture, usually referred to as piezoelectric effect or electrostriction phenomenon, as shown in Figure 3. This failure mode is still the limiting factor faced by multilayer ceramic capacitor manufacturing to date. It affects most barium titanate Class II dielectrics and limits the capacitance range of ceramic capacitors with a size of more than 1210 and a withstand voltage of more than 200V.

As shown in Figure 3, the fracture usually runs through the middle of the capacitor along one or two dielectric layers. Most solutions are to stack multiple capacitors by adding pins to increase the capacitance under a given size, but this requires a lot of manpower, costs more, and creates reliability issues. Other solutions use special dielectric formulations, but at the expense of dielectric constant and the final capacitance value that can be obtained.

 

 

 

 

Deformation of X7R multilayer ceramic capacitors under DC bias

Solution

StackiCapTM is a monolithic capacitor solution to address piezoelectric failure limitations. Its patented technology GB Pat./EP2013/061918 innovatively adds a pressure buffer layer inside the capacitor, allowing the capacitor to exhibit the performance of multiple stacked capacitors while also having the advantages of a single capacitor in terms of manufacturing and processing.

 

The pressure buffer layer uses a combination of off-the-shelf material systems and goes through a standard manufacturing process. The pressure buffer layer is added to one or more locations where the mechanical stress is the greatest, thereby alleviating the mechanical stress caused by piezoelectric deformation. According to experiments so far, the pressure buffer layer can divide the multilayer capacitor into 2, 3 or 4 sections internally, thereby greatly alleviating the mechanical stress caused by internal deformation, and at the same time release the mechanical stress on the end through FlexiCap flexible end technology, so that we do not need to stack multiple capacitors, and we no longer need to assemble pins for the capacitors, which facilitates standardized tape packaging and automated mounting.

 

 

Cross section of the “sponge” pressure buffer layer (SEM micrograph)

Miniaturization

While greatly increasing the capacitance, StackiCapTM can significantly reduce the size of components. The following pictures intuitively show the advantages of StackiCapTM.

Figure 7 shows the sizes of the various specifications of the StackiCapTM products that have been developed: 1812, 2220, 2225 and 3640. Figure 8 shows a pin capacitor assembly with up to 5 capacitors stacked, with single capacitor sizes of 2225, 3640, 5550 and 8060. Figures 9 and 10 show the capacitor assemblies that can be replaced by a single StackiCapTM capacitor. An extreme example is that a 8060, 1kV, 470nF capacitor can now be replaced by a single 2220, 1kV, 470nF StackiCapTM; a 3640, 1kV, 180nF capacitor can now be replaced by a single 1812, 1kV, 180nF StackiCapTM, reducing the volume to 1/10 and 1/7 of the original size respectively.

 

 

 

 

 

 

 

 

Reliability testing and certification

StackiCap has passed the following reliability tests:

(1) Life test: StackiCap series capacitors are tested at 125°C and 1 or 1.5 times the rated voltage for 1000 hours.

(2) 85/85 test. StackiCap series capacitors are subjected to continuous operation at 85°C/85%RH for 168 hours.

(3) Bend Test. StackiCap series capacitors are mounted on a Syfer/Knowles test PCB and subjected to a bend test to evaluate the mechanical properties of the components.

Reference address:Capacitor solutions for piezoelectric failure

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