Design solution based on MCU and USB device controller IP core

1 Introduction

Serial ports (such as RS232) and parallel ports are often used to connect peripheral devices in traditional computer systems. However, both serial ports and parallel ports have insurmountable disadvantages such as slow communication speed and interface monopoly that is not conducive to expansion. The Universal Serial Bus (USB) has been widely used due to its advantages such as fast transmission speed, hot plug support, convenient expansion, strong anti-interference, low cost, high data transmission quality, and saving system resources. It has now become one of the most commonly used computer interfaces.

There are two main types of USB controllers now: microcontrollers (MCUs) with USB interfaces and pure USB interface chips. Pure USB interface chips only handle USB communications and must have an external microprocessor to perform protocol processing and data exchange. Typical products include Philips' PDIUSBD11 (I2C interface) and PDIUSBD12 (parallel interface); NS's USBN9603/9* (parallel interface). Microcontrollers with USB interfaces can be divided into two categories based on application. One is a microcontroller designed from the bottom layer for USB control; the other is an ordinary microcontroller with an added USB interface, such as Cypress's EZ-USB (based on 8051). The biggest advantage of choosing this type of USB controller is that developers are very familiar with the system structure and instruction set, and the development tools are simple, but the price is relatively high, which is not conducive to product upgrades and modifications.

However, the USB chips used in domestic products are all imported, mainly provided by foreign IC design chip manufacturers such as Cypress, NEC and other internationally renowned companies. In view of the good market prospects and profit margins of USB chips, although domestic enterprises or research institutions are still at the technical level of USB chip application development, people still hope to independently develop USB chips with independent intellectual property rights. Therefore, in recent years, many domestic units have also been exploring independent design of USB chips.

This paper targets the USB1.1 protocol specification and develops a USB control chip independently. It integrates the MCU and USB device controller on a chip in the form of a soft core. The microcontroller uses a 14-bit instruction word length, and is a single-byte instruction and a single-cycle instruction. There are only 39 core instructions, which are easy to master and design, and fully meet the requirements of the overall design.

2 MCU&USB device controller working principle and overall design

The overall structure of the whole design is shown in Figure 1. The differential signal lines D+ and D- are connected to the host. When receiving, the serial data sent by the host is decoded and checked by the transceiver and USB device controller and then stored in the corresponding RAM; when sending, the arbitration module controls the extraction of the corresponding data from the RAM or ROM and sends it to the host serially through the USB device controller combination and the transceiver. The MCU mainly assists the USB controller to complete the data transmission between the device and the host.

2.1 MCU Design

MCU mainly completes various interrupt processing, and assists the controller to enable the host to detect and identify the device; when the device is just plugged into the PC, the MCU initializes the dedicated function register by reading the instructions in the ROM, enabling the global interrupt GIE and USB interrupt USBint, so that the controller can respond to various USB interrupts in time; when the global interrupt enable bit GIE is set, all interrupts are allowed; when cleared, all interrupts are prohibited. When an interrupt is responded to, the GIE bit is cleared to prohibit other interrupts, and the interrupt service program is loaded, and the interrupt return address is pushed into the stack. The interrupt flag bit that causes the interrupt service program to be loaded is cleared by software before re-enabling GIE to avoid repeated interrupt responses. In the interrupt service program, the interrupt source can be determined by detecting the interrupt flag bit, and the setting of each interrupt flag bit is not affected by GIE; in the process of communication between the device and the host, the MCU handles the interrupt processing of setup packets, in packets, out packets, ack, nak, stall packets, etc. We have specified the interrupt entry addresses of USB interrupts, timer interrupts, external interrupts, and GPIO interrupts as 04H, 08H, 0CH, and 10H respectively; the MCU also performs corresponding operations on each function register, such as writing the maximum value allowed for the input and output packets of endpoint 0, the data trigger bit DSQ (i.e., Data Toggle mechanism), etc.

2.2 Design of arbRAM and arbROM (arbitration module)

The design contains two kinds of memories: program memory (ROM) and data memory (SRAM). Both memories have their own buses. In one clock cycle, both memories can be accessed at the same time. Both USB and MCU can access SRAM and ROM. The arbitration module is set up to avoid conflicts when both are accessed at the same time; USB accesses the address space 100h-fffh of ROM (we store the device descriptor here), and USB access only takes the lower 8 bits of 14-bit width data. When USB and MCU access ROM at the same time, MCU has priority. USB and MCU share general registers (SRAM). When the USB request to access the memory signal arrives, the upper three bits of the address signal of USB accessing the memory are not equal to zero, which belongs to the address space of USB accessing the program memory. When USB and MCU access general registers (SRAM) at the same time, MCU has priority.

2.3 Design of USB device controller

The USB device controller is the key part of the design and the focus of this paper. The overall module division is shown in Figure 2;

2.3.1 Transceiver Design

As the analog front end of the USB interface, the USB transceiver mainly converts the analog signal sent by the host into digital signals VP and VM and transmits them to the digital phase-locked loop or converts the VP0 and VM0 digital signals sent by the protocol engine into analog signals and completes the serial-to-parallel and parallel-to-serial conversion.

The transceiver model is shown in Figure 3. Dplus is the positive phase USB differential data line, and Dminu is the negative phase USB differential data line, both of which are bidirectional. OEn is the USB transmit enable. When it is low, it functions as a transmit function, and the single-phase output port is set to high impedance. When it is high, it functions as a receive function, and the single-phase input port is set to high impedance.

2.3.2 Dpll (Digital Phase-Locked Loop) Module

The digital phase-locked loop realizes clock recovery, frequency division and clock synchronization; the module uses the external 6M clock CLK for frequency division to generate a 1.5M USB system clock, and phase-locks the differential signal and parallel signal generated by the transceiver to avoid metastable state.

2.3.3 SIE (Serial Interface Engine) Module

SIE is the main module of the USB controller; it implements the functions of the protocol layer, parsing and combining of information packets, synchronization signal recognition, bit filling and bit stripping, NRZI (non-return-to-zero inverted) encoding and decoding, detection and generation of synchronization fields and packet end codes, CRC5, CRC16 checking and other functions; Figure 4 is the state machine when the device receives data sent by the host.

From Figure 4, it can be seen that the device is in the idle state when there is no data transmission. When the low-speed device is idle, D+ and D- are in the J state. When the K state arrives, it enters the state transition; KJKJKK is the synchronization bit. The last 2 bits in the synchronization field are the mark of the end of the synchronization field and mark the beginning of the packet identifier (PID, Packet Identifier). Then, according to different PIDs, it enters the address state or data state respectively. Immediately following the address state is the endpoint state. Because the address and endpoint are 7 bits and 4 bits respectively, a total of 11 bits, only 5 bits of CRC check are needed. After the CRC check, the packet transmission will end. In the USB protocol, 2 SE0 states and one J state are used to indicate the end of the packet. In the data state, it is determined whether it is the SE0 state. The SE0 state indicates that all 8 bytes of data have been sent. Because the non-SE0 state, that is, the J and K states, both indicate the working state, in the data state, if there is no SE0 on the bus, data will be received continuously.

2.3.4 ENDPCTL (Endpoint Control) Module

Two endpoints are used in the design, endpoint 0 and endpoint 1. Endpoint 0 is half-duplex transmission, mainly used for control transmission during device enumeration, and endpoint 1 is used for data transmission between the device and the host in interrupt transmission after enumeration. Since interrupt transmission is mainly input through endpoint 1, but there are also a few outputs (such as the LED light output of the keyboard), in order to save resources, we use endpoint 0 to complete a few outputs.

2.3.5 BUFCTL (Buffer Control) Module

The buffer control module is the bridge between USB, SRAM and ROM. When the host requests to input data in the IN token state, the controller takes data from SRAM or ROM and sends it to the host. When the host outputs data in the OUT token state, the controller stores the received data in SRAM. It mainly controls the read and write signals according to the receive or send ready signals of the serial interface engine SIE to ensure that the data can be transmitted correctly. USB and MCU share the general register area. usbREQUST is the request access memory signal from USB, usbADDR is the address signal of USB access memory, and usbADDR[11:8] belongs to the address space of USB access program memory when it is not equal to zero. When USB and MCU access data memory (SRAM) at the same time, MCU has priority.

3 System Verification Environment

After completing the Verilog code design, we conducted simulation and synthesis verification, using Modelsim for pre-simulation, Synplify Pro for synthesis, and NC_Verilog in Cadence for post-synthesis simulation, mainly because NC_Verilog is faster than Modelsim in post-simulation, which improves efficiency. Figure 5 shows the enumeration process of NC_Verilog simulation equipment;

Any USB data transmission is based on successful enumeration. Only when enumeration is completed correctly can the communication between the USB host and the device be established. Therefore, enumeration is the most critical step in USB communication. In the verification process, the PC host is simulated to send various commands to the device to complete the enumeration. In Figure 5, D, 3, 9, 2, 1, and B in pid[3:0] represent Setup, DATA0, IN, Ack, Out, and DATA1 respectively. When the device is plugged into the PC, the host will continue to reset the device with SE0. At this time, the device address defaults to 00. Then the host sends the Setup packet for the first time to obtain the first 8 device descriptors of the device. When the device successfully returns data, the host sends the Setup packet for the second time to configure the device address. From the figure faddr[7:0], we can see that the address we configure for the device is 02. After that, the host uses this address to obtain all 18 device descriptors and all configuration descriptor sets from the device. After obtaining these descriptors, the host configures the device and the host recognizes the device.

4 Conclusion

This paper describes the design ideas of the self-developed MCU+USB device controller. It is described at the RTL level in Verilog language. Modelsim is used for pre-simulation verification, and the synthesis post-simulation verification is passed on Cadence's NC_Verilog. In order to further verify the correctness of the design, this project selected the Virtex xc2s2006pq208 chip and XC18V02 memory of XILINX, and synthesized the above IP cores into this FPGA for verification. The synthesis results show that the protocol layer module occupies 1672 slices (71%), 652 slice registers (13%), 2870 4-input LUTs (61%), and 51 bonded IOBs (36%). Using Shanghua technology, the chip has been returned and connected to the PC through a demo board. The PC can detect that it is a human input device, indicating that the chip fully meets the established design requirements.