Application Design of Improved CMOS Charge Pump Phase-Locked Loop Circuit

In this paper, a CMOS phase-locked loop (PLL) circuit with a wide frequency range is designed. By improving the current mirror image accuracy of the charge pump circuit and adding a switching noise cancellation circuit, the phase deviation problem caused by current mismatch, charge sharing, clock feedthrough, etc. in the traditional circuit is effectively improved.

A frequency multiplication control unit is designed. By programming the frequency multiplication factor and the transconductance of the voltage-controlled oscillator delay unit, the frequency locking range of the phase-locked loop is effectively expanded. The circuit is designed based on the Dongbu HiTek 0.18μm CMOS process. The simulation results show that under the working voltage of 1.8 V, when the output voltage of the charge pump circuit changes from 0.25 to 1.5 V, the charge pump's charge and discharge current consistency is very good. Within the output frequency range of 100 MHz to 2.2 GHz, the frequency capture time is less than 2μs, and the steady-state relative phase error is less than 0.6%.

A phase-locked loop (PLL) is a closed-loop negative feedback system that can accurately generate a series of frequency signals in phase with the reference frequency. It is one of the indispensable systems in modern communications and electronics, and is usually used for frequency synthesis, synchronous signal generation, clock recovery, and clock generation. Charge pump phase-locked loop (CPPLL) is now widely used in the field of wireless communications because of its advantages such as large open-loop gain, wide capture range, fast capture speed, high stability, and small phase error.

1 System structure and working mechanism

The charge pump phase-locked loop is usually composed of a phase frequency detector (PFD), a charge pump circuit (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (FD). The structure of the phase-locked loop system designed in this paper is shown in Figure 1. The specific working principle of the loop is: by detecting the phase difference and frequency difference between the reference signal fref at the input end of the PFD and the loop feedback signal fdiv, the corresponding voltage signals VUP and VDN are output to control the working state of CP. The charge pump circuit converts the UP and DN signals into the control voltage VC output of the voltage-controlled oscillator. VC filters out the high-frequency components through the LPF and outputs a DC level, which is finally used as the control signal of the voltage-controlled oscillator. As the frequency difference and phase difference between the two input signals of the phase frequency detector continue to decrease, when VC is a certain constant voltage value, the loop reaches a locked state.

Figure 1 Charge pump phase-locked loop structure

A multiple frequency control (MFC) module is added during the design and used in conjunction with the frequency divider and voltage-controlled oscillator. Through the logic input of the control bit, on the one hand, the frequency lock multiple can be programmed to control the frequency multiple of the entire loop; on the other hand, the transconductance of the VCO differential delay unit can be controlled, thereby changing the voltage gain of the VCO to adjust its output range.

Figure 2 shows the linear equivalent model of the circuit in Figure 1. In the figure: Ip is the charge pump current; F(s) is the filter transfer function; KVCO is the gain of the voltage controlled oscillator; N is the frequency division ratio; φin is the input reference phase; φout is the output phase; φdiv is the feedback phase after frequency division.

Figure 2 Linear equivalent model of charge pump phase-locked loop

The open-loop transfer function H(s) of the entire system can be deduced as

Where s is the complex variable in the Laplace transform, and the filter transfer function F(s) can be further expressed as

Where: R, C1 and C2 are the corresponding resistance and capacitance values ​​in Figure 1. It can be seen from formula (2) that the filter transfer function F(s) is a second-order linear system. For a second-order linear system, the denominator of its transfer function can be expressed as ζ2+2ζωn+ωn2, where ωn is the natural frequency and ζ is the damping coefficient. In order to reduce the jitter of the loop and ensure the stability of the loop operation, the loop natural frequency ωn is generally designed to be 1/10~1/20 of the reference frequency, and the damping coefficient ζ is designed to be 0.3~0.7.

2 Charge Pump Circuit Design

The conventional charge pump circuit is shown in FIG3 . The current source Iref provides mirror currents IUP and IDN proportional to Iref to M2 and M7 through current mirroring. The output logic signals VUP and VDN of the PFD control the on and off of the switch tubes M3 and M4 . M3 and M4 are alternately turned on to charge and discharge the filter capacitor CC to obtain the charge pump output voltage VC . However , due to some non - ideal factors of MOS devices and circuit structures , the circuit has problems such as charge and discharge current mismatch , charge sharing and clock feedthrough .

Figure 3. Conventional charge pump circuit for phase-locked loop

The charge and discharge current of the traditional charge pump circuit is provided by a common current mirror, where M1 and M2 form a charge current mirror, and M5 and M7 form a discharge current mirror. Ideally, the charge and discharge currents can remain consistent. However, the current mirror MOS device working in the saturation region is affected by the channel length modulation effect, and the mirror current will change with the change of the source-drain voltage difference. Specifically, on the one hand, the mirror current of M6 and M7 will be different due to their different drain voltages, which will cause different charge and discharge currents of the charge pump; on the other hand, when the VC voltage changes within a certain range, the charge and discharge currents output by M2 and M7 cannot remain consistent.

The phase error caused by current mismatch can be expressed as

Where: ICP is the set charge pump current; ΔICP is the mismatch current of the charge pump; Δton is the on-time generated by the PFD circuit; Tref is the reference period. It can be seen from the above formula that the influence of the current mismatch value on the phase error is proportional, so it is particularly important to eliminate the current mismatch in the charge pump circuit.

There are also charge sharing and clock feedthrough effects in the charge pump charge and discharge cycle. When charging, M3 is turned on, the drain voltage of M2 is reduced to the VC value, while M4 is turned off, and the drain voltage of M7 is reduced to zero; when discharging, M3 is turned off, the drain voltage of M2 is increased to the VDD value, while M4 is turned on, and the drain voltage of M7 is increased to the VC value. Since there are parasitic capacitances in the drains of M2 and M7, they will absorb and release charges during the charge and discharge cycle, thus affecting the output of the charge pump. This phenomenon is called charge sharing. In addition, during the charge and discharge cycle, the parasitic capacitances of the gates of M3 and M4 will also release and absorb charges under the drive of the clock signal, thereby affecting the output of the charge pump. This phenomenon is also called clock feedthrough.

Aiming at the problems of current mismatch, charge sharing and clock feedthrough existing in the traditional charge pump circuit, this paper proposes an improved charge pump circuit, as shown in FIG4 .

Figure 4 Improved charge pump circuit for phase-locked loop

As shown in Figure 4, in order to suppress the switch tube clock feedthrough phenomenon, the positions of the switch tubes M8 and M2 and the current mirror tubes M6 and M4 are swapped, which can effectively reduce the change amplitude of the switch tube drain voltage. At the same time, the switch tubes M1, M7 and M9 are added to match M2, M8 and M10 respectively to eliminate the error of the current mirror.

In addition, the added switch tubes M11 and M12 are turned on in anti-phase with M8 and M2 respectively, so that the charges generated by the clock feedthrough and charge sharing phenomenon can be offset.

In order to solve the problem of current mirror mismatch, negative feedback is used to suppress the mismatch of charge and discharge current mirror. Specifically, M5, M6 and M10 form a current mirror to mirror the reference current Iref, and then M6 outputs the charge current of the charge pump. The drain current of M5 flows through M3, and then the current mirror formed by M3 and M4 outputs the discharge current of the charge pump through M4. The introduction of amplifier OP forms negative feedback at the VX node, which can strictly ensure that VX=VC, thus almost completely eliminating the mismatch of charge and discharge current caused by the difference in drain voltage of the current mirror.

In addition, the drains of the switch tubes M11 and M12 are connected to the VX node. Since VX=VC, the drain voltages of M11 and M12 are also equal to VC. This not only matches the charges generated by the clock feedthrough and charge sharing phenomenon, but also avoids the influence of the drains of M11 and M12 directly connected to VC on the charge pump output.

The amplifier OP adopts a rail-to-rail structure to ensure the swing range of the input and output voltages, so as to increase the linear range of the charge pump output voltage. The introduction of capacitor C1 not only stabilizes the negative feedback loop, but also filters the VX voltage glitch interference.

3. Circuit design of other modules

3.1 Voltage Controlled Oscillator

Since the folded differential ring voltage-controlled oscillator has a simple circuit structure, good control linearity and low noise, the voltage-controlled oscillator designed in this paper is implemented using a four-stage differential delay structure. The circuit structure is shown in FIG5 .

Figure 5 Voltage controlled oscillator circuit

The voltage-controlled oscillator differential delay unit is shown in FIG6 . The linearity and delay time range of the delay unit determine the linearity and frequency range of the voltage-controlled oscillator. In order to maximize the use of the range of the charge pump output voltage to improve the noise suppression capability of the phase-locked loop, a piecewise linear method is used in the design of the voltage-controlled oscillator delay unit to divide the delay time into three sections for control. The control voltage VC controls the gate voltages of MOS tubes M7, M8 and M9 respectively to form three different currents to control the linear range of the delay unit. Among them, M10, M11 and M12 are controlled by the logic signal generated by the MFC unit in FIG1 as switch tubes, and one of the current paths is selected according to the different frequency ranges. In order to improve the linearity of the controlled current with the control voltage VC, source negative feedback resistors are added to M7, M8 and M9, and the optimized resistance values ​​are verified to be 0.4, 5 and 50 kΩ respectively. In addition, in order to increase the operating frequency of the voltage-controlled oscillator, the number of M7 tubes is increased. The number of M7 tubes selected in the design is 4 times that of M8 and M9. In addition, a buffer stage is added to the last stage of the delay unit to convert the double-ended output into a single-ended output.

3.2 Phase and frequency detector

The phase-frequency detector circuit is shown in Figure 7. It consists of two D flip-flops with reset function. A transmission gate unit is added to the signal path to match the delay between the UP and DN control signals. The circuit uses a high level to achieve reset, and the phase detection range is -2π~2π. By changing the size of the inverter, the reset pulse delay width can be adjusted, the phase detection dead zone can be eliminated, and the phase detection accuracy can be improved.

Figure 6 Voltage controlled oscillator differential delay unit

Figure 7 Frequency and phase detection circuit

4 Results Analysis

The charge pump phase-locked loop circuit proposed in this paper is designed based on Dongbu HiTek 0.18 μm CMOS process and is simulated and verified in detail using the Hspice model.

Figure 8 is the simulation result of the charge pump charge and discharge current matching under the typical model. The simulation results show that the charge pump charge and discharge current consistency is very good when the output voltage changes from 0.25 to 1.5 V. Table 1 shows the relative mismatch (or relative error δi, expressed in percentage) of the charge pump charge and discharge current under different process angles and different output voltages. It can be seen from the data in Table 1 that the improved charge pump circuit in this paper effectively suppresses the mismatch of the charge and discharge current.

Figure 8. Charge pump current matching simulation results.

Table 1 Relative mismatch of charge pump charge and discharge current at different process angles (δi)

Figure 9 shows the simulation results of the relationship between the control voltage and output frequency of the voltage-controlled oscillator. It can be seen from the figure that according to the different output frequencies, the delay unit produces three different linearities, corresponding to the current paths connected to 0.4, 5 and 50 kΩ resistors in Figure 6. The linear range can be roughly divided into: 25~120 MHz is the first section; 120~650 MHz is the second section; 650 MHz~2.2 GHz is the third section. The linear range of the first and second stages is relatively wide, and the linear range of the third stage decreases after entering the high frequency, but overall the adopted segmented linear control achieves a good effect.

Figure 9 Relationship between control voltage and output frequency of voltage-controlled oscillator

Figure 10 shows the simulation waveform of the phase-locked loop establishment process. The figure shows the waveform of the VCO control voltage. When the input reference frequency is 31.5 MHz and the frequency feedback is set to 32 division, the system locking time is about 1.5μs. The use of the MFC module and the piecewise linear processing of the voltage-controlled oscillator effectively expand the locking range, and the output frequency is adjustable within 25 MHz~2.2 GHz. In practical applications, more output frequencies can be obtained by selecting commonly used crystal oscillator frequencies and integer division multiples. Figures 11 and 12 respectively show the change curves of the phase-locked loop capture time tcap and the steady-state relative phase error δp when the output frequency changes from 100 MHz to 2.2 GHz. The results show that in the output frequency range of 100MHz~2.2GHz, the phase-locked loop capture time is less than 2μs and the phase error is less than 0.6%.

Figure 10 Transient simulation waveform of the phase-locked loop establishment process

Figure 11 Capture time (tcap) vs. output frequency

Figure 12. Corresponding relationship curve between steady-state relative phase error (δp) and output frequency

5 Conclusion

In the entire charge pump phase-locked loop system, the charge pump circuit plays a very critical role. The traditional charge pump circuit has some non-ideal factors that directly affect the working performance of the entire loop, such as charge leakage, current mismatch, charge sharing, clock feedthrough, etc., which will cause the output frequency of the voltage-controlled oscillator to jitter and phase deviation.

The high-performance CMOS charge pump phase-locked loop circuit designed in this paper improves the matching of charge and discharge currents by improving the traditional charge pump circuit, effectively suppresses the phase deviation of the phase-locked loop output, and improves the stability of the loop. At the same time, the frequency multiplication control module MFC and the voltage-controlled oscillator segment processing are added to the loop to effectively expand the frequency locking range. The circuit is designed based on the Dongbu HiTek 0.18μm CMOS process and has been fully simulated and verified. The results show that when the output frequency changes within 100 MHz~2.2 GHz, the frequency locking time and phase error are effectively controlled, verifying the effectiveness of the design.