How to choose the right MOSFET for your power system switching controller?

　　MOSFET selection for DC/DC switching controllers is a complex process. Considering only the voltage and current ratings of the MOSFET is not enough to select the right MOSFET. To keep the MOSFET within the specified range, a balance must be struck between low gate charge and low on-resistance. This becomes even more complicated in multi-load power supply systems.

　　DC/DC switching power supplies are widely used in many modern electronic systems due to their high efficiency. For example, a buck synchronous switching regulator with both a high-side FET and a low-side FET is shown in Figure 1. The two FETs switch according to the duty cycle set by the controller to achieve the desired output voltage. The duty cycle equation for the buck regulator is as follows:

　　Figure 1: Step-down synchronous switching regulator schematic

　　The FETs may be integrated into the same chip as the controller, which provides the simplest solution. However, to provide high current capability and/or achieve higher efficiency, the FETs need to remain external to the controller. This allows for maximum heat dissipation because it physically isolates the FETs from the controller and provides the most flexibility in FET selection. The downside is that the FET selection process is more complex because there are many factors to consider.

　　A common question is “Why won’t this 10A FET also work for my 10A design?” The answer is that this 10A current rating is not appropriate for all designs. Factors to consider when selecting a FET include voltage rating, ambient temperature, switching frequency, controller drive capability, and heat sink area. The key issue is that if the power dissipation is too high and the heat sink is insufficient, the FET may overheat and catch fire. Users can estimate the junction temperature of a FET using the package/heat sink component ThetaJA or thermistor, FET power dissipation, and ambient temperature as follows:

　　Other losses are caused by output parasitic capacitance, gate losses, and body diode losses due to conduction during the low-side FET dead time, but this article will focus on AC and DC losses.

　　This is shown highlighted in Figure 2. According to Equation 4, one way to reduce this loss is to shorten the rise and fall times of the switch.

　　Figure 2: AC loss diagram

　　This can be achieved by selecting a FET with a lower gate charge. Another factor is the switching frequency. The higher the switching frequency, the greater the percentage of the switching time spent in the rising and falling transition regions shown in Figure 3.

　　Figure 3: Effect of switching frequency on AC losses

　　Therefore, higher frequency means greater AC switching losses. So, another way to reduce AC losses is to reduce the switching frequency, but this requires larger and usually more expensive inductors to ensure that the peak switch current does not exceed the specification.

　　DC losses occur when the switch is in the on state due to the on-resistance of the FET. This is a fairly simple I2R loss mechanism as shown in Figure 4. However, this is further complicated by the fact that the on-resistance varies with the FET junction temperature.

　　Figure 4: DC loss diagram

　　Therefore, an iterative approach must be used to accurately calculate the on-resistance using equations 3, 4, and 5, taking into account the temperature rise of the FET. The simplest way to reduce DC losses is to select a FET with a low on-resistance. In addition, the amount of DC losses is directly proportional to the percentage on-time of the FET, which is the high-side FET controller duty cycle plus 1 minus the low-side FET duty cycle, as previously described. As can be seen in Figure 5, longer on-time means greater DC switching losses, so DC losses can be reduced by reducing the on-time/FET duty cycle. For example, if an intermediate DC voltage rail is used and the input voltage can be modified, the designer may be able to modify the duty cycle.

　　Although choosing a FET with low gate charge and low on-resistance is a simple solution, there are some trade-offs and balances between these two parameters, as shown in Figure 6. Low gate charge generally means smaller gate area/fewer parallel transistors, and thus higher on-resistance. On the other hand, using larger/more parallel transistors generally results in low on-resistance, which results in more gate charge. This means that FET selection must balance these two conflicting specifications. In addition, cost factors must also be considered.

　　Figure 6: Comparison of on-resistance and gate charge for some new FETs that effectively balance these two parameters

　　Low duty cycle designs mean high input voltages, and for these designs, the high-side FET is mostly off, so DC losses are low. However, high FET voltages result in high AC losses, so a FET with low gate charge can be chosen, even though the on-resistance is high. The low-side FET is mostly on, but the AC losses are minimal. This is because the voltage across the low-side FET during on/off is very low due to the FET body diode. Therefore, a FET with low on-resistance needs to be chosen, and the gate charge can be high. Figure 7 shows this.

　　Figure 7: High-side and low-side FET power dissipation for a low duty cycle design

　　If the input voltage is reduced, a high duty cycle design can be obtained where the high-side FET is on most of the time, as shown in Figure 8. In this case, the DC losses are higher and a low on-resistance is required. Depending on the input voltage, the AC losses may not be as important as for the low-side FET, but they are still not as low as for the low-side FET. Therefore, a suitably low gate charge is still required. This requires a compromise between low on-resistance and low gate charge. For the low-side FET, the on-time is minimized and the AC losses are low, so the right FET can be selected based on price or size rather than on-resistance and gate charge.

　　Figure 8: High-side and low-side FET power dissipation for a high duty cycle design

　　Assuming a point-of-load (POL) regulator can specify a nominal input voltage for an intermediate voltage rail, what is the best solution, high input voltage/low duty cycle or low input voltage/high duty cycle? Create a design in TI's WEBENCH Power Designer and use this as an example. Modulate the duty cycle with different input voltages and look at the FET power dissipation. In Figure 9, the high-side FET response curve shows that the AC loss decreases significantly when the duty cycle goes from 25% to 40%, while the DC loss increases linearly. Therefore, a duty cycle of about 35% should be the ideal value for selecting a FET with balanced capacitance and on-resistance. Continuously reducing the input voltage and increasing the duty cycle can get the lowest AC loss and the highest DC loss. In this regard, a low on-resistance FET can be used and a high gate charge can be selected.

　　Figure 9: High-side FET losses vs. duty cycle

　　As shown in Figure 10, DC losses decrease linearly as the controller duty cycle increases from low to high (the low-side FET is on for a shorter time), with losses being minimal at high controller duty cycles. The AC losses of the entire board are low, so FETs with low on-resistance should be selected in all cases.

　　Figure 10: Low-side FET losses vs. controller duty cycle

　　Figure 11 shows how the total efficiency changes when we combine the high-side and low-side losses. You can see that in this case, the combined FET losses are lowest and the efficiency is highest at high duty cycles. The efficiency increases from 94.5% to 96.5%. Unfortunately, to get low input voltages, the intermediate voltage rail supply must be stepped down, increasing its duty cycle since it is powered from a fixed input supply. Therefore, this may negate some or all of the gains made at the POL. Another approach is to not use the intermediate rail and go directly from the input supply to the POL regulator in order to reduce the regulator count. In this case, the duty cycle is lower and the FETs must be carefully selected.

　　Figure 11: Total losses vs. efficiency and duty cycle

　　The situation is more complicated in power systems with multiple output voltage and current requirements. The WEBENCH Power Designer tool can be used to visualize the trade-offs in such systems. This tool allows users to see various scenarios using different intermediate rail voltages and compare the efficiency, cost, and size of different POL regulator duty cycles. Figure 12 shows a system with an input voltage of 28V and a total of 8 loads with 4 different voltages ranging from 3.3 to 1.25V. There are three comparison methods: 1) no intermediate rail, providing 28V directly from the input power supply to achieve a low duty cycle for the POL regulator; 2) using a 12V intermediate rail and a medium duty cycle for the POL regulator; 3) using a 5V intermediate rail and a high POL regulator duty cycle.

　　Figure 12: Power system showing input, mid-rail, point-of-load (POL) supply, and load

　　Figure 13 and Table 1 show the results. In this case, the architecture with no intermediate rail achieves the lowest cost, the architecture with 12V intermediate rail voltage achieves the highest efficiency, and the architecture with 5V intermediate rail voltage achieves the smallest size. Therefore, we can see that for this large system, there is no clear trend in these parameters as seen in the single POL supply case. This is because when using multiple regulators, in addition to the intermediate rail regulator itself, each regulator has its own different load current and voltage requirements, which may conflict with each other. The best way to study this situation is to use a tool such as WEBENCH Power Designer to evaluate different options.

　　Figure 13: WEBENCH power design curve

　　Table 1: Impact of intermediate rail voltage on power system efficiency, size and cost

　　In short, FET selection is a complex task, but if the right choice is made, a low-cost, high-efficiency power system can be achieved. Tools such as WEBENCH Power Design can help users visually compare different methods, make trade-offs and balanced choices, and quickly obtain an ideal design.