How to design and test field effect transistor integrated circuits?

　　The advent of FinFETs has a significant impact on the physical design and testability design flow of integrated circuits . The introduction of FinFETs means that complementary metal oxide semiconductor (CMOS) transistors must be modeled as three-dimensional (3D) devices in the integrated circuit design process, which includes various complexities and uncertainties. The BSIM Group of the Device Group at the University of California, Berkeley, has developed a model, called the BSIM-CMG (common multi-gate) model, to represent the resistance and capacitance of FinFETs. Wafer foundries strive to provide accurate device and parasitic data, while also working to retain the models used by previous processes.

　　Parasitic Extraction Challenges

　　However, each foundry modifies the standard model to more closely represent its specific architecture and process. In addition, at these advanced process nodes, foundries want their “golden” models, built with reference field solvers, to correlate more closely with the results obtained by designers in the field using extraction tools. At the 28nm node, foundries want commercial extraction tools to be between 5% and 10% accurate to their golden models. For FinFET processes, foundries require a mean accuracy error of less than 2% between commercial extraction tools and the golden model, with a 3x discrete standard deviation of only 6%-7%.

　　The most challenging task is to calculate the parasitic data between the FinFET and its surroundings, which requires accurate 3D modeling of the front-end-of-line (FEOL) geometry. Ensuring accuracy in three dimensions requires extraction using a 3D field solver. 3D field solvers were previously used for process characterization rather than design because they were too expensive and too slow to compute. Now a new generation of 3D extraction tools, such as Mentor's Calibre xACT, run an order of magnitude faster than before by using self-adjusting meshing technology to accelerate calculations. It also has a highly scalable architecture that can take advantage of modern multi-CPU computing environments. With these capabilities, extraction tools can easily execute field solver calculation solutions on 32 CPU machines, ranging from a few cells to blocks with millions of embedded transistors.

　　At the full chip level, we need to consider billions of transistors and tens of millions of interconnects, and even fast field solvers cannot offer a practical turnaround time. The solution is to use advanced heuristics, using field solvers for complex structures and table-based extraction methods for general geometries. This approach is feasible because the electric field model in the wiring grid is similar to that seen at previous process nodes. In the best case, the extraction model used by designers will not change, because the extraction tool will automatically move between field solvers and table methods.

　　As double and triple masks play an increasingly important role in manufacturing starting at the 20nm node, we are experiencing a leap in the number of interconnect corners. At 28nm, 5 interconnect corners were possible, however, for 16nm, we expect to need 11-15 corners. Advanced multi-corner analysis programs enable more efficient calculations, reducing the amount of additional calculations required for each additional corner. In addition, we can process the corners in parallel so that each additional corner only increases the overall turnaround time by 10%. This means that 15 corners only require 2.5 times the run time of a single corner.

　　Testing Challenges

　　Test and failure analysis are particularly important because the critical dimensions of FinFETs are, for the first time, much smaller than the underlying node dimensions. This makes the challenges of increasing defect levels and increasing yield increasingly concerning. Cell-Aware test methods are particularly well suited to address these issues because they can target defects at the transistor level. In contrast, traditional scan test patterns can only identify defects in the interconnects between cells. The cell-aware analysis process establishes a fault model based on the simulated behavior of defects within the cell layout. The result is the production of higher quality graphics vectors. When cell-aware methods are used to automatically generate test graphics vectors (ATPG), silicon verification results show that significantly more additional defects are detected from technology nodes from 350 nanometers to FinFET levels, beyond fixed modes and transition modes.

　　Consider a multi-fin field-effect transistor with three fins. Recent research suggests that such transistors should account for two defect types: leakage defects that cause partial or full breakdown of the transistor, and drive strength defects that cause the transistor to be partially or completely shut down.

　　Figure 1: Testing for leakage defects in FinFETs

　　Leakage defects can be analyzed by placing resistors across the gates (from drain to source) of each transistor's 3 fins, as shown in Figure 1. During the cell identification analysis, analog simulations are performed on all resistors with different resistor values ​​for all FinFETs in a given cell library. Defects are modeled by the transistor's response delay at a certain gate threshold. Drive strength defects can be analyzed by placing resistors between the drain and each gate and between the source and the gate. As for leakage testing, analog simulations are performed by varying the resistance value of each resistor. The difference in response time for each fin is used to determine if defect modeling is required. Other FinFET defect types can be handled in a similar way.

　　FinFETs do present some new challenges, but EDA tool vendors and foundries are doing their best to integrate solutions with minimal impact on the IC design process.