Editor's recommendation: Using simplis to verify the DCM of loop theory

Now let's look at the DCM Buck :

The duty cycle is still 0.5, the output load is 100 ohms, and the operating frequency is 500Khz.

Let's calculate Re first. According to the formula, we can get Re=80, then M=0.66, output voltage V=0.66*50=33, and we can calculate the DC gain (from duty cycle to output) Gd0=30.5db;

The low-frequency pole is 12.6Hz, and the zero point brought by ESR is still 16Khz; from an application perspective, this is enough.

From an academic point of view, we can also calculate the high-frequency pole, and the result is 618Khz.

Such a high frequency has exceeded the switching frequency, but the actual low-frequency small signal model must be much lower than the switching frequency.

The model itself is completely inaccurate when approaching or exceeding the switching frequency, so this result has no practical significance.

Take a look at the simulation results:

Simulation results:

The DC gain is about 30db, the pole is about 10Hz, and the zero point is between 10Khz and 20Khz, which is consistent with the theory .

The duty cycle is 0.5 and the output load is 300 ohms;

Let's calculate first: Re=80, M=2.5, V=125, Gd0=45.5db; the pole position is 2.8Hz, of course, the zero point caused by esr is still at 16Khz; calculate the high-frequency pole and the right half plane zero

Pole: 477KHz, RHP zero: 318KHz so you can ignore them.

Simulation results:

DCM buckboost

According to the above formula: Re=80, M=-1.58, V=-79, Gd0=44db, pole: 3.18Hz

Also look at the high frequency pole, 503K; RHP zero, 318K Naturally ignore them

Finally, let’s take a look at the results