Introduction to the basics of power grid

　　Voltage drop (IR) on the VDD network and ground bounce on the VSS network can affect the entire timing and functionality of the design, and if their existence is ignored, it is likely to cause the failure of the chip design. High current in the power grid can also cause electromigration (EMI) effects, which can cause metal line performance degradation in the power grid during the normal life of the chip. These adverse effects will eventually cause costly field failures and serious product reliability issues.

　　IR Drop and Ground Bounce in Power Grids

　　The reason for the IR drop on the VDD network is that the operating current of the transistor or gate flows from the VDD I/O pin through the RC network of the power grid, which causes the VDD voltage reaching the device to drop. Ground bounce is similar to this phenomenon. When the current flows back to the VSS pin, it also passes through the RC network, which causes the VSS voltage reaching the device to rise. More sophisticated design processes and next-generation design technologies have made new designs more vulnerable to IR drop or ground bounce. IR drop on the power grid mainly affects timing. It will reduce the drive capability of the gate and increase the delay of the entire path. Generally, a 5% drop in supply voltage will increase the delay by more than 15%. The delay of the clock buffer will increase by more than 1 times due to IR drop. When the clock skew range is within 100ps, such a delay increase will be very dangerous. You can imagine what kind of scenario will happen if this unexpected delay occurs on the critical path of the centralized configuration. Obviously, the performance or function of the design will become unpredictable. Ideally, to improve the accuracy of the design, its timing calculation must take into account the worst-case IR drop.

　　There are two main methods for power grid analysis: static and dynamic.

　　Static Power Grid Analysis

　　Static power grid analysis methods provide comprehensive coverage without the need for additional circuit simulation. Most static analysis methods are based on the following basic concepts:

　　1. Extract the parasitic resistance of the power grid;

　　2. Establish the resistance matrix of the power grid;

　　3. Calculate the average current for each resistor or gate connected to the power grid;

　　4. Distribute the average current into the resistor matrix based on the physical location of the transistors or gates;

　　5. Apply VDD source to the matrix on each VDD I/O pin;

　　6. Calculate the current and IR drop through the resistor matrix using the static matrix solution.

　　Since the static analysis method assumes that the decoupling capacitors between VDD and VSS are sufficient to filter out dynamic peaks of IR drop or ground bounce, its results are very close to the effects of dynamic switching on the power grid.

　　The main value of static analysis lies in its simplicity and comprehensive coverage. Since only the parasitic resistance of the power grid is required, the extraction effort is very small. And each transistor or gate provides an average load to the power grid, so this method can fully cover the power grid, but its main challenge is accuracy. Static analysis does not consider local dynamic effects and package conduction effects (Ldi/dt), both of which will cause further IR drop and ground bounce if there is not enough decoupling capacitance on the power grid.

　　Dynamic Power Grid Analysis

　　The dynamic power grid analysis method requires not only the extraction of the parasitic resistance of the power grid, but also the extraction of the parasitic capacitance, and the completion of the dynamic circuit simulation of the resistor RC matrix. The typical steps of the dynamic power grid analysis method are:

　　1. Extract the parasitic resistance and capacitance of the power grid;

　　2. Extract the parasitic resistance and capacitance of the signal network;

　　3. Extract the design netlist;

　　4. Generate a circuit netlist based on the extracted parasitic resistance, capacitance and netlist;

　　5. Perform circuit simulation based on the simulation vector set, mainly simulating the dynamic switching of transistors or gates and the impact of this switching on the power grid.

　　The main value of dynamic analysis is its accuracy. Since the analysis is based on circuit simulation, the IR drop and ground bounce results will be very accurate and take into account local dynamic effects and package conduction effects.

　　However, the challenges faced by dynamic analysis are also very daunting, because:

　　1. Parasitic extraction is very demanding, as the resistance and capacitance of the power grid and (at least) the capacitance of the signal net need to be extracted.

　　2. There are a lot of objects in circuit simulation, which will make the circuit simulation engine work at full capacity.

　　3. The vector set used as stimulus plays an important role in determining the quality of the output. If a complete test vector set is not employed, the results will be questionable as some parts of the power grid may not be simulated.

　　4. Finally, because there are so many considerations for a single power grid, power grid analysis based on comprehensive dynamic simulation will have difficulty adapting to further increases in design size.

　　Many power grid analysis methods that pursue dynamic effects must resort to RC compression technology to manage large amounts of simulation data, but this is inconsistent with the main value of dynamic analysis methods - high accuracy. RC compression of the power grid will lead to a decrease in the accuracy of the analysis results and even cover up the real EMI problem.

　　Electromigration and full-chip EMI analysis

　　Electromigration of the power grid is a DC phenomenon caused by the average current flowing through the metal lines and vias. This is another important problem that arises in deep submicron power grid design. High current density and narrow line width will cause EMI, and failures caused by EMI can be catastrophic. These failures usually occur at the user's side, when the chip has already been installed on the substrate in the system. If a problem really occurs, it may cause the design to be recalled.

　　Although EMI can cause opens or shorts in the power grid, the most common effect is the increase in resistance in the power grid path, which causes IR drop or ground bounce, affecting the timing of the chip. This is also the reason why a design works properly and meets specifications at first, but later fails. The guiding basis for EMI design is the average current level, which ultimately depends on the capacitance of the signal line.

　　Therefore, accurate EMI prediction requires correct capacitance information. In addition, since the metal lines in the design will have different height variations and metals have different levels of material properties, each metal layer will have different failure criteria, so the only way to determine all areas with potential EMI problems on the entire chip is to perform a full chip analysis.

　　The industry often uses Black's law to predict the mean time between failures of metal lines. The main parameter is the average current density J shown next to the metal line. The more accurate the average data, the better the MTTF estimation effect. In order to obtain the most accurate data information, it is often necessary to use a large number of vectors in the design. At the same time, the average current of each metal line must be measured and then divided by the width and thickness of the line. This is obviously impossible to do when constructing a chip, and it cannot be achieved using circuit simulation.

　　Another alternative to expensive transistor-level simulation is to use gate-level or higher-level tools to extract average current from activity information in the form of toggle data. Toggle data is simply the number of times a gate switches high or low during a simulation cycle of thousands of clocks. Dividing this toggle data by the number of clock cycles gives activity information. For example, the activity of a memory circuit core may be 0.02%, while a data path may be closer to 5%. For transistors connected to the power grid, these factors can be converted into average current information.

　　Of course, designers must determine the average current flowing on the entire power grid in order to assess the reliability risk of a given design. It is not enough to simply determine the average behavior of an isolated module, because the module may only work periodically during the full chip flow. In addition, even a change to a part of the power grid will have an impact on the whole. Data compression cannot be used because data compression itself may mask some real EMI problems. Therefore, unless the entire chip is fully verified as an entity, there is still a risk of insufficient EMI prediction accuracy. Any tool used for this purpose must be able to analyze millions of resistor networks.

　　Power grid analysis has become a critical design verification part before tapeout. The design of IC power distribution system has become extremely complex due to the existence of IR voltage drop, ground bounce and EMI. In the early days, DRC, LVS and manual calculation of the power grid can ensure a perfect power grid design, and spending more effort on power grid design was considered an acceptable solution. In today's fiercely competitive market, too much consideration of the power grid will lead to reduced yield and uncompetitive design, while insufficient consideration will lead to tapeout failure, tapeout iterations and costly field failures - you can't have the best of both worlds.