A circuit design of low voltage and low quiescent current LDO (I)-EEWORLD

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With the rapid development of handheld smart terminals in the past few decades, low drop-out linear regulators (LDOs) have been widely used due to their advantages such as low power consumption, high power supply rejection ratio, small size, and simple circuit design. LDOs work in low-load applications most of the time, so their quiescent current consumption under low-load conditions determines the life of the battery. Today's LDO development trend is to extend battery life with low voltage and low quiescent current. However, low quiescent current can lead to instability and large output voltage transient changes, and a reasonable compromise must be made between quiescent current and output transient characteristics. Compared with the traditional LDO that uses a discrete bandgap reference voltage source and error amplifier, this paper presents an innovative structure of LDO, which combines the two modules of bandgap reference voltage source and error amplifier into one, so it is easier to achieve low quiescent current consumption and low transient voltage changes.

1 LDO circuit analysis

Figure 1 shows a simplified LDO structure, which includes only four main current branches: a gain stage, a buffer stage, and two PTAT current sources.

Compared with the traditional LDO structure, the streamlined structure combines the bandgap reference voltage source and the error amplifier into one, so the circuit static current consumption can be reduced to about 1/2 of the original while other performance remains unchanged.

This circuit has two disadvantages: the output voltage is a bandgap reference voltage and cannot be adjusted; it requires the use of NPN transistors, which do not exist in standard CMOS processes. Since today's SoCs tend to work in low-voltage environments, this structure can be used in a variety of applications. The second problem is that when designing a single chip, using a double-well CMOS process, only one mask process needs to be added, and the cost increase is not much, so the two problems are not obvious in practical application.

1.1 Bandgap reference voltage analysis

The transistor base-emitter voltage and thermodynamic voltage have negative and positive temperature coefficients respectively. Therefore, the principle of the bandgap reference voltage is to superimpose the transistor base-emitter voltage and the thermodynamic temperature voltage to achieve a zero temperature coefficient at room temperature.

In the simplified LDO structure, transistor Q3 and resistor R2 define the bandgap reference voltage, and the current flowing through R2 is the PTAT current. The current flowing through transistor Q1 is mirrored. Transistor Q3 is biased to the collector current. Therefore, in the loop, transistors Q1 and Q3 will be adjusted to the same base-emitter voltage value. This adjustment is quite accurate, especially in the case of high loops. Therefore, by properly designing resistors R2 and R3, transistors Q1, Q2 and Q3 have the same collector current. Therefore:

Where: IS is the transistor saturation current; β2 is the current gain of transistor Q2; n is the emitter area ratio of transistor Q2 and Q1. The PTAT current can be obtained by equation (1):

Therefore, the output voltage value can be obtained by superimposing the base-emitter voltage of transistor Q3 and the voltage of R2:

Adjust the resistance ratio to make the VT coefficient

When the value is 17.2, a bandgap reference voltage with a temperature coefficient of zero can be obtained.

1.2 LDO frequency analysis

The simplified structure LDO contains three low-frequency poles, which are located at the output of the gain stage, the output of the buffer stage and the output node of the LDO, as follows:

In the formula: ro1 and C1 are the gain stage output resistance and load capacitance respectively; ro2 is the buffer stage output resistance; Cpar is the power tube parasitic capacitance; rop is the equivalent resistance of the LDO output stage; CL is the output load compensation capacitance. In order to ensure that the LDO has a good output transient characteristic, the CL value is generally large, so the pole p3 is the main pole of the LDO loop. The collector current of transistor Q3 is biased as PTAT current, so the output impedance of the gain stage does not change much with the output load current and input voltage. At the same time, the load capacitance of the gain stage is mainly determined by the buffer stage input capacitance, so the position of the pole p1 is relatively stable, so a left half plane zero point compensation can be used. Similar to the traditional LDO, this article uses a resistor resr in series with the output compensation capacitor to obtain a left half plane zero point:

Based on the above analysis, the open-loop transfer function of the simplified structure LDO is:

In the formula

.Where: gmQ2, gmQ3 and gmp represent the transconductance of transistors Q2, Q3 and power tube respectively; Rπ 3 is the input resistance of transistor Q3. When p1 and z1 match more accurately, the LDO loop has only two low-frequency poles p2 and p3. Therefore, in order to obtain a phase margin of 60°, it is necessary to:

Reference address：A circuit design of low voltage and low quiescent current LDO (I)

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