More and more applications, such as process control and weighing, require high-resolution, high-integration and low-cost ADCs. The new Σ-Δ conversion technology can meet these requirements. However, many designers do not know much about this conversion technology, so they prefer to use traditional successive comparison ADCs. The analog part of the Σ-Δ converter is very simple (similar to a 1-bit ADC), while the digital part is much more complex and can be divided into digital filtering and extraction units according to function. Since it is closer to a digital device, the manufacturing cost of the Σ-Δ ADC is very low.

　　1. Working Principle of Σ-Δ ADC

　　To understand how Σ-Δ ADCs work, it is important to first understand the following concepts: oversampling, noise shaping, digital filtering, and decimation.

　　1. Oversampling

　　First, consider the frequency domain transfer characteristics of a traditional ADC. A sinusoidal signal is input and then sampled at a frequency of fs - according to the Nyquist theorem, the sampling frequency must be at least twice the input signal. From the FFT analysis results, we can see a single tone and a series of random noises with frequencies distributed between DC and fs /2. This is the so-called quantization noise, which is mainly caused by the limited ADC resolution. The ratio of the amplitude of the single tone signal to the sum of the RMS amplitudes of all frequency noises is the signal-to-noise ratio (SNR). For an Nbit ADC, the SNR can be obtained by the formula: SNR=6.02N+1.76dB. In order to improve the SNR and reproduce the input signal more accurately, the number of bits must be increased for traditional ADCs.

　　If we increase the sampling frequency by an oversampling factor k, that is, the sampling frequency is kfs, we can discuss the same problem again. FFT analysis shows that the noise baseline is reduced, the SNR value remains unchanged, but the noise energy is dispersed to a wider frequency range. The Σ-Δ converter uses this principle, and the specific method is to perform digital filtering immediately after the 1-bit ADC. Most of the noise is filtered out by the digital filter, so that the RMS noise is reduced, so that a low-resolution ADC, Σ-Δ converter can also obtain a wide dynamic range.

　　So, how does simple oversampling and filtering improve SNR? The SNR of a 1-bit ADC is 7.78dB (6.02+1.76). Every 4-fold oversampling will increase the SNR by 6dB. Every 6dB increase in SNR is equivalent to an increase in resolution of 1 bit. Thus, a 1-bit ADC with 64-fold oversampling can achieve 4-bit resolution; to achieve 16-bit resolution, 415-fold oversampling is required, which is impractical. Σ-Δ converters use noise shaping technology to eliminate this limitation, increasing the signal-to-noise ratio by more than 6dB for every 4-fold oversampling factor.

　　2. Noise shaping

　　The working mechanism of noise shaping can be understood by looking at the working principle of the first-order Σ-Δ modulator shown in Figure 1.

Figure 1 Sigma-Delta Modulator

　　The Σ-Δ modulator consists of a differential amplifier, an integrator, a comparator, and a feedback loop consisting of a 1-bit DAC (a simple switch that can connect the inverting input of the differential amplifier to a positive or negative reference voltage). The role of the feedback DAC is to make the average output voltage of the integrator close to the reference level of the comparator. The density of "1"s in the modulator output will be proportional to the input signal. If the input voltage increases, the comparator must produce a greater number of "1"s, and vice versa. The integrator is used to sum the error voltage, acting as a low-pass filter for the input signal and a high-pass filter for the quantization noise. In this way, most of the quantization noise is pushed to a higher frequency band. Compared with the previous simple oversampling, the total noise power has not changed, but the distribution of the noise has changed.

　　Now, if the noise shaped sigma-delta modulator output is digitally filtered, it is possible to remove more noise than with simple oversampling. This modulator (first order) provides a 9dB improvement in SNR for every doubling of the oversampling ratio.

　　Using more integration and summation stages in the Σ-Δ modulator can provide higher order quantization noise shaping. For example, a second-order Σ-Δ modulator can improve the SNR by 15dB for every doubling of the oversampling rate. Figure 2 shows the relationship between the order of the Σ-Δ modulator, the oversampling rate, and the achievable SNR.

Figure 2 Relationship between SNR and oversampling rate

　　3. Digital filtering and decimation

　　The Σ-Δ modulator outputs a 1-bit data stream at a sampling rate that can be as high as MHz. The purpose of digital filtering and decimation is to extract useful information from this data stream and reduce the data rate to a usable level.

　　The digital filter in the Σ-Δ ADC averages the 1-bit data stream, removes out-of-band quantization noise and improves the ADC's resolution. The digital filter determines the signal bandwidth, settling time, and stop-band rejection.

　　A widely used filter topology in sigma-delta converters is the SINC3, a filter with a lowpass characteristic. One of the main advantages of this filter is the notch characteristic, which can be set at the same frequency as the power line to suppress interference from it. The notch is directly related to the output data rate (the inverse of the conversion time). The settling time of the SINC3 filter is three times the conversion time. For example, with the notch set at 60Hz (60Hz data rate), the settling time is 3/60Hz = 50ms. Some applications require faster settling time, but lower resolution requirements. For these applications, new ADCs such as the MAX1400 series allow the user to select the filter type SINC1 or SINC3. The settling time of the SINC1 filter is only one data period, which is 1/60Hz = 16.7ms for the previous example. Since the bandwidth is reduced by the output digital filter, the output data rate can be lower than the original sampling rate and still meet the Nyquist theorem. This is achieved by keeping some samples and discarding others, a process called "decimation" by a factor of M. The M factor is the decimation ratio and can be any integer value. The decimation factor should be chosen so that the output data rate is greater than twice the signal bandwidth. Thus, if the input signal is sampled at a frequency of fs, the output data rate after filtering can be reduced to fs/M without losing any information.

        2. MAXIM's new Σ-Δ ADC

　　New highly integrated Σ-Δ ADCs are gaining more and more applications. This type of ADC can directly process weak signals with very few external components. The MAX1402 is an example of this new generation of ADCs. Most of the signal processing functions have been integrated into the chip, which can be regarded as a system on a chip, as shown in Figure 3. The device can provide 16-bit accuracy at a working rate of 480sps, 12-bit accuracy at 4800sps, and consumes only 250μA of current in operating mode and only 2μA in power-down mode. The signal path includes a flexible input multiplexer that can be set to 3 fully differential signals or 5 pseudo differential signals, 2 chopper amplifiers, 1 programmable PGA (gain from 1"128), 1 coarse DAC for eliminating system offsets, and 1 second-order Σ-Δ modulator. The 1-bit data stream generated by the modulator is sent to an integrated digital filter for fine processing (configured as SINC1 or SINC3). The conversion results can be read through an SPITM/QSPITM compatible three-wire serial interface. In addition, the chip also includes 2 fully differential input channels for system calibration (offset and gain); 2 matched 200μA current sources for sensor excitation (for example, can be used for 3-wire/4-wire RTD); 2 "pump-out" currents for detecting the integrity of the selected sensor. The operating mode of the device can be programmed by accessing 8 on-chip registers inside the device through the serial interface. The input channel can be sampled or continuously sampled under the control of an external command, which is set by the SCAN control bit. A 3-bit "channel identification" bit is added to the conversion result to determine the input channel.

Figure 3 MAX1402 block diagram

　　Two additional calibration channels, CALOFF and CALGAIN, can be used to calibrate the measurement system. In this case, the CALOFF input can be connected to ground and the CALGAIN input can be connected to a reference voltage. The measurement results of the above channels can be averaged and used to calibrate the measurement results.

　　3. Application of Σ-Δ ADC

　　1. Thermocouple measurement and cold junction compensation

　　As shown in Figure 4, in this application, the MAX1402 operates in buffer mode to allow the use of relatively large decoupling capacitors on the front end (to eliminate noise picked up by the thermocouple leads). To accommodate the common-mode range of the input buffer, a reference voltage is used to bias the AIN2 input. When using thermocouples to measure temperature, cold-junction compensation is necessary to obtain accurate measurement results. The output voltage of the thermocouple can be expressed as

V = α (t1-tref)

　　Where α is the Seebeck constant related to the thermocouple material, t1 is the temperature to be measured, and tref is the temperature at the junction box. In order to compensate for the error caused by tref, diode compensation can be used at the output of the thermocouple; or the temperature at the junction box can be measured and then compensated by software. In this example, the differential input channels AIN3 and AIN4 are used to measure the temperature of the PN junction (biased with an internal 200μA current source).

Figure 4 Thermocouple measurement and cold junction compensation

　　2.3-wire and 4-wire RTD measurements

　　Platinum resistance temperature sensors (RTDs) are preferred by many applications that require temperature measurement because of their excellent accuracy and interchangeability. An RTD with a resistance of 100Ω at 0°C will reach 200Ω at +266°C, with a very low sensitivity of approximately ΔR/Δt=100Ω/266°C. An excitation current of 200μA can produce a 20mV output at 0°C and a 40mV output at +266°C. The MAX1402 can directly process this low-level signal.

　　Depending on the application, lead resistance can have varying degrees of impact on measurement accuracy. Generally speaking, if the RTD is close to the converter, the simplest two-wire configuration is sufficient; when the RTD is far away, lead resistance will be superimposed on the RTD impedance and introduce significant errors to the measurement results. In this case, a 3-wire or 4-wire RTD configuration is usually used, as shown in Figure 5.

Figure 5 3-wire and 4-wire RTD measurements

　　The two matched 200μA current sources inside the MAX1402 can be used to compensate for the errors caused by lead resistance in a 3-wire or 4-wire RTD configuration. In a 3-wire configuration, two matched 200μA current sources flow through RL1 and RL2 respectively, so that the differential voltage at AIN1 and AIN2 will not be affected by the lead resistance. This compensation method is valid only if the two leads are made of the same material and have the same length, and the temperature coefficients of the two current sources are precisely matched (5×10-6/℃ for MAX1402). Lead resistance will not introduce any errors in a 4-wire configuration because there is basically no current flowing in the measurement leads connected to AIN1 and AIN2. In this configuration, current source OUT1 is used to excite the RTD sensor and current source OUT2 is used to generate a reference voltage. In this ratiometric configuration, the temperature drift error of the RTD (caused by the temperature drift of the RTD excitation current) is compensated by the drift of the reference voltage.


　　3. Intelligent 4" 20mA transmitter

　　The old 4"20mA transmitter uses a field-mounted sensitive element to sense some physical information, such as pressure or temperature, and then generates a current proportional to the physical quantity to be measured. The current range is standardized to 4"20mA. The current loop has many advantages: the measurement signal is not sensitive to noise; it can be easily powered remotely. The second generation of 4" 20mA transmitters perform some signal processing at the remote end, usually using a microcontroller and data converter, as shown in Figure 6. This transmitter first digitizes the signal, then processes it using algorithms built into the microcontroller, normalizes the gain and zero point, linearizes the sensor, and finally converts the signal to the analog domain and transmits it through the loop as a standard current. The third generation of 4" 20mA transmitters, which are called "smart and intelligent", actually add digital communication to the previous functions (sharing the same twisted pair as the traditional 4" 20mA signal). Some control and diagnostic signals can be transmitted using the communication channel. Low-power devices such as the MAX1402 are very suitable for this application, and the 250μA power consumption can save considerable power for the rest of the transmitter circuitry. The communication standard used by smart transmitters is the Hart protocol. This is a Bell-based 202 telecommunications standard communication protocol, operating in frequency shift keying (FSK). The digital signal consists of two frequencies: 1200Hz and 2200Hz, corresponding to digital 1 and 0 respectively. The two frequency sine waves are superimposed on the DC analog signal and transmitted simultaneously through the same cable. Because the average value of the FSK signal is always zero, the 4"20mA analog signal will not be affected. Without interfering with the analog signal, the digital communication signal has a response speed of 2"3 data updates per second. The minimum loop impedance required for communication is 23Ω.

 

Figure 6 Intelligent 4" 20mA transmitter

　　summary

　　Before the advent of highly integrated conditioning systems, process control typically used multiple separate chips for signal conditioning and processing. Σ-Δ technology reduces the cost, space requirements, and power requirements of this part of the circuit (in fact, most applications only need a single +3V/+5V supply). This feature is particularly suitable for battery-powered portable systems. The reduction in component count also improves system reliability.