Portable power engineering design

Providing mobility to products can bring additional benefits and open up new markets outside of existing applications. The portable ultrasound device market is a good example. Until now, ultrasound imaging examinations have required going to a clinic. In most developed countries, this is usually not a problem. However, in some remote villages and towns, if the equipment can be transported directly to the patient, it will greatly improve the local medical environment. When designing mobile devices, the trade-offs between weight, size and operating time are extremely challenging. When conventional power conversion efficiency exceeds 90%, many engineers will choose to redesign the circuit board and strive to find greater efficiency improvement space from different functional perspectives to reduce overall power consumption.

Pick low-hanging fruit first

Generally speaking, looking for power gain opportunities should start from the most obvious or easiest place. When the power conversion efficiency is between 60% and 75%, the largest power gain first comes from the conversion from linear regulator to switching regulator, which will greatly improve the overall efficiency of the system. Today, integrated high-efficiency switching regulators are available, and engineers must seek new breakthroughs beyond power conversion.

Size, weight, heat dissipation and cost are all driving factors in the mobile market, and these factors often influence the decision-making process. Currently, the battery is the weak link in the system and cannot keep up with the development of semiconductor process technology. As modern power supplies continue to improve in energy efficiency, the next opportunity to reduce power losses will come from the system structure itself. In recent years, Intel and other CPU manufacturers have gradually realized that speeding up the CPU may not be the best way to improve performance. The main problems they face are the heat generated by the processor and the dynamic requirements of peripheral devices. Gradually migrating to multi-core architectures and providing operating systems that support multi-core will enable more significant performance gains (while reducing power consumption).

Just as CPU vendors no longer improve performance by changing megahertz numbers, mobile product designers should re-examine how they implement related functions. One area where architectural changes are beginning to occur is in analog-to-digital conversion (ADC). For example, National Semiconductor has innovated the use of integrated folding converters to not only greatly increase operating speed (gigasamples per second) but also minimize energy consumption during operation. Traditional flash-based converters are limited by the maximum number of comparators that can be integrated, which is a function of the number of output bits (2n bits). For example, a 10-bit flash DAC would require 1,024 comparators, plus thermometer code to Gray code to binary conversion circuitry and a high-precision unified ladder resistor divider.

The folding converter is based on a completely different design approach, using a small number of comparators (typically 32 to 64) and “folding” the input signal range so that it always stays within the limits of the comparator network, as shown in Figure 1. The trick here is to compensate for the integral and differential nonlinearities introduced by the folding process. This structure represents a completely new way of thinking about this thorny problem and greatly reduces the energy consumption required to implement this function. For a dual 10-bit converter (PowerWise ADC10D1000) that samples at gigasamples per second, this approach can reduce power consumption from tens of watts to three watts. This is a common power-saving measure in portable imaging, radar, and software-defined radio systems.

Digital Power Architecture

In large ASIC or SoIC designs, architecture is equally important. Even when shrinking the process geometry, dynamic and static losses associated with CMOS transistors are a constant problem. The energy consumption formula for CMOS is as follows:

E = (aCfCLKV2 + VILEAK) × tTASK

It includes a frequency-dependent dynamic term and a static leakage term. Both parameters become problematic as process geometries continue to shrink. Capacitive loading and shoot-through currents will decrease, but the number of components on the chip will increase, resulting in higher dynamic power consumption per chip. Static losses caused by subthreshold leakage, drain-source extended leakage, electron tunneling, and short channel effects such as drain-induced barrier lowering (DIBL) are becoming increasingly serious issues in large digital ASIC designs.

When designing large digital systems, timing must be set correctly throughout the entire operation, including supply voltage, process and temperature fluctuations. Such design bottlenecks make power consumption at the worst level, even at the right temperature or faster process, the device will still consume the same energy. One solution is to change the design structure to adapt it to the environment of the device. Adaptive voltage scaling (AVS) is a technology to achieve this goal.

AVS integrates a digital subsystem that monitors the operating status of the device (it is synchronized with the application digital logic) and dynamically adjusts the supply voltage of different voltage islands inside the chip. When performance requirements change, the AVS logic inside the chip sends an update signal to the external power management device, which is called the energy management unit EMU. Its function is to increase or decrease the supply voltage of the voltage island. The dynamic term is a square function of the supply voltage, so it can provide the greatest gain improvement. Even if the static term is only a linear function of the supply voltage, the reduction in leakage current can still significantly reduce energy consumption.

In order to save as much energy as possible, the design structure once again shows its importance. In order to maximize the effectiveness of AVS or other voltage scaling techniques, system designers must rethink the division of functional areas and provide separate voltage islands and frequency regions. If the existing design uses a single voltage source to power all core logic, then multiple voltage islands should be adopted in the new low-power design, where the clock region will become the limiting factor of dynamic requirements. Moreover, due to slower timing, these voltage islands can take advantage of voltage scaling techniques or simply use lower core voltages.

There is an increasing demand for portability, especially in the medical, communications and military defense fields. Engineers need to consider solutions beyond power converters to seek greater system efficiency gains. From a system architecture perspective, sometimes innovative means are taken to implement certain functions - especially when conventional power converter efficiencies are above 90%, which can often lead to huge efficiency improvements. Power technology will eventually catch up with technological advances in process flow and IC design, but until engineers have higher energy density, system efficiency remains one of the solutions to extend operating time and reduce heat consumption.