Generates a pulse with a width inversely proportional to the square root of the analog voltage

The circuit in Figure 1 is an edge-triggered monostable circuit based on a previous design of an edge-triggered parabolic pulse generator (Reference 1). This circuit makes a simple but significant change to the earlier generator, that is, the input terminal consisting of S2 and IC3 (see the original design) of the first stage of the cascaded integrator is disconnected from the reference voltage source VREF and connected to the input voltage terminal in Figure 1.

Figure 1. A low-to-high transition at the clock input triggers the monostable. The pulse width produced at the complementary Q and Q outputs is a mathematically nonlinear function of the 0V to 3V analog input voltage.

The output pulse width on the output Q of this circuit is:

Although the monostable function is implemented with this modification, another function is added to the IC 1, IC 2, and IC 3 logic circuits in Figure 1. The added logic ensures that the generator ignores trigger pulses that arrive while the monostable is busy.

In this way, the integrator capacitor of the generator can be discharged to nearly 0V with an error of no more than 0.4%, even at relatively high trigger frequencies exceeding the value of 1/[TQ(VIN)]. Therefore, the output pulse width for a certain input voltage is constant, even if the trigger period is very close to or less than the output pulse width.

The subcircuit composed of IC1 and IC2 generates an RST (reset) signal, whose trailing edge determines the end of a monostable operation cycle. The RST signal in this circuit prohibits the re-triggering of the monostable during the transition of the Q output from low to high and the transition of the RST signal from high to low. To this end, the clock of the trigger signal is ORed with the RST signal in IC3 (Figure 2).

Figure 2. The high level of the generated RST logic signal prevents any low-to-high transition at the clock input from triggering the monostable unless the generator's integrator is reset in a determined manner.

Thus, after the trailing edge of the RST pulse, the next valid trigger is enabled. The leading edge of the RST pulse occurs approximately when the quadratic parabola voltage VOQ reaches half of its peak voltage VPEAK. When VOQ falls below VPEAK / 2, the trailing edge of the RST pulse is delayed. The auxiliary time constant (RD + RS)CD of the RS/CD/RD network at the input of IC1A defines this delay. Experimental evaluation shows that the relative error of the output pulse width is:

The error amplitude then increases, reaching a maximum of δTQ = -2.337 × 10-3 at an input voltage of 99.925 mV. By further reducing the input voltage, the magnitude of the negative error decreases, reaching δTQ = -1.113 × 10-3 at an input voltage of 9.915 mV. At an input voltage of 3.08 mV, the relative error is positive, δTQ ≈ 2.9 × 10-3. Further reducing the input voltage causes the positive error to increase rapidly, reaching 3% at an input voltage of 1.065 mV. Note, however, that the input voltage span is almost 3000:1. The trigger frequency is 2 Hz or 200 Hz.

The pulse widths obtained are almost the same when the trigger frequency is 2kHz, 200kHz, and 2MHz. The pulse width variation due to the trigger frequency variation can be comparable to or even lower than the delta TQ value. For a full-scale input, when the input voltage is equal to the reference voltage, the measured pulse width is 445.44μs.

Using the VOQ output, the circuit can also be used as a precision quadratic parabola time-base generator; the input voltage controls the speed of the generator.