Power supply design tips: Pay attention to the SEPIC coupled inductor loop current (1)

In this Power Tip, we will determine some leakage inductance requirements for coupled inductors in the SEPIC topology. The SEPIC is a very useful topology when electrical isolation between the primary and secondary circuits is not required and the input voltage is either higher or lower than the output voltage. It can be used in place of a boost converter when short-circuit protection is required. The SEPIC converter features single-switch operation and continuous input current, resulting in low electromagnetic interference (EMI). This topology (shown in Figure 1) can use two separate inductors (or, since the voltage waveforms of the inductors are similar, a coupled inductor, as shown in the figure). Coupled inductors are attractive because they are smaller and less expensive than two separate inductors. The disadvantage is that standard inductors are not always optimized for all possible applications.

Figure 1. The SEPIC converter uses a switch to raise or lower the output voltage.

The current and voltage waveforms of this circuit are similar to the continuous current mode (CCM) flyback circuit. When Q1 is turned on, it uses the input voltage of the coupled inductor primary to build up energy in the circuit. When Q1 is turned off, the voltage of the inductor is reversed and then clamped to the output voltage. Capacitor C_AC is what differentiates the SEPIC from the flyback circuit; when Q1 is on, the secondary inductor current flows through it and then to ground. When Q1 is off, the primary inductor current flows through C_AC, increasing the output current through D1. A big benefit of this topology over the flyback circuit is that both the FET and diode voltages are clamped by C_AC, and there is very little ringing in the circuit. This allows us to choose to use lower voltage and therefore more power efficient devices.

Since this topology is similar to the flyback topology, many would think that a tightly coupled set of windings is required. However, this is not the case. Figure 2 shows the two operating states of a continuous SEPIC, where the transformer has been modeled by leakage inductance (LL), magnetizing inductance (LM), and an ideal transformer (T). Upon inspection, the voltage across the leakage inductance is equal to the voltage across C_AC. Therefore, a large AC voltage with a small value of C_AC or a small leakage inductance will form a large loop current. Large loop currents reduce the efficiency and EMI performance of the converter, which is undesirable. One way to reduce this large loop current is to increase the coupling capacitor (C_AC). However, this comes at the expense of cost, size, and reliability. A more sophisticated approach is to increase the leakage inductance, which can be easily achieved if a custom magnetic component is specified.

2a) MOSFET on: VLL = VC_AC - VIN = ∆VC_AC (DC part removed)

2b) MOSFET off: VLL = VIN + VOUT - VC_AC - VOUT = ∆VC_AC (DC portion removed)

Figures 2a and 2b show the two operating states of the SEPIC converter.

The AC voltage across the leakage inductance is equal to the coupling capacitor voltage.

Interestingly, very few manufacturers have realized this fact, and many have produced inductors with low leakage inductance for SEPIC applications. On the other hand, Coilcraft has a 47 uH MSD1260 with about 0.5 uH leakage inductance, and has recently developed other versions of this design with leakage inductances of more than 10 uH, which we will introduce in the next "Power Design Tips", so stay tuned.