An effective method for bridging circuits powered by different power supplies

As transistors become smaller, the operating voltage is also getting lower. In the past, the most common application in embedded systems was 5V power supply. However, most components in a typical embedded system have also moved to lower supply voltages to take advantage of the latest industry trends. On the other hand, some components in the system take longer to complete the transition. Therefore, during the transition, some components in the system may require different supply voltages (such as 5V devices in a 3.3V system and vice versa). This brings some design challenges to embedded designers. One solution is to use a logic level converter, but using a level converter is not the most cost-effective solution. This article will discuss some low-cost design ideas for interfacing 3.3V microcontrollers (MCUs) with 5V peripherals.

If you want to convert a 5V design to 3.3V, the first thing to do is to look for a microcontroller that has the same performance as a 3.3V power supply. In most cases, you can find an equivalent device that supports 3.3V. And, basically, the cost of 3.3V devices is the same or even lower. If you can't find an alternative device that can run under 3.3V conditions, then you must use dual power supplies. This article focuses on designs that use dual power supplies.

For designs where 5V and 3V devices coexist, you must first understand the logic levels and input/output structure. For inputs, you need to consider VIH (the voltage that is guaranteed to be detected as a high input) and VIL (the voltage that is guaranteed to be detected as a low input). When connecting a 3.3V system to a 5V device, VIH usually causes a bigger problem than VIL. Of course, this does not mean that the VIL parameter can be ignored. The driver device must output a voltage higher than the VIH(min) value of the receiving device to ensure correct logic detection. However, if the voltage is too high, it is not good either.

几乎所有CMOS器件在所有I/O引脚都采用了某种形式的ESD保护。实现ESD保护最常见的方法是采用箝位二极管将这些引脚连接到Vdd 和 Vss。这通常意味着最大输入电压为Vdd +0.3V，最小输入电压为Vss - 0.3V。如果电压超出这一范围，保护二极管就会导通。如果输入端没有串联电阻，就会导致这些二极管通过极大电流，并有可能造成器件锁死。这肯定不是所希望发生的。如果电压足够高(如3.3V系统中的5V输入)，那么串联电阻必须非常大才能保证箝位电流处于安全范围内。如果电阻足够大，那么由于引脚电容和PCB布线而引起的低输入容抗可能就会变得重要起来。RC时间常数会导致信号延迟。许多生产商都建议不要使用箝位二极管实现ESD保护。因此，采用串联电阻并非将5V信号馈送到3.3V器件的最好方法。

Let's look at the logic levels of standard CMOS devices. Most devices have a VIH (min) of 0.7 Vdd or 0.8 Vdd. The VIL (max) is roughly 0.2 Vdd or 0.3 Vdd. For 5V logic, the corresponding VIH is 3.5V or 4.0V, and the VIL (max) is 1.0V or 1.5V. At light load, the output of most CMOS devices is close to the supply voltage (0.1 or 0.2V). As the load current increases, VOH will become lower. At this time, the load current must be considered when determining VOH.

A better approach than using a series input resistor is to use a resistor divider to convert the 5V signal to a 3.3V input range (see Figure 2). The resistor value must be chosen to take into account all tolerances. The following formula can be used for calculation:

R2/(R1 + R2)×VOH (min)＞VIH(min) (Input voltage is the sum of the nominal value 5 V and the maximum negative tolerance)

R2/(R1 + R2)×VOH (max)

The tolerance of the resistor value itself should also be taken into account in the above calculation process.

Another simpler solution is to use a 5V device with TTL compatible input. The VIH(min) of a TTL device is 2.1V (at 5V Vdd). Most 3.3V devices can support a higher VOH level under large load conditions. In this case, the solution is to replace the peripheral device with an equivalent device with TTL compatible input.

It should be easy to find similar devices with TTL inputs. Table 1 gives some examples.

If you are using a standard digital logic family device that must be powered by 5V, then you can look for an equivalent device that supports TTL inputs. (For example, you can use the 74HCT series instead of the 74HC series.) If you need to use a level shifter, you can use a "HCT" or "VHCT" type digital buffer. In most cases, this TTL input solution is cheaper than using a dedicated level shifter.

The VOH level of a 3.3V device is generally slightly lower than the VIH of a 5V CMOS device (0.7Vdd = 3.5V). A simple solution is to use diodes to achieve voltage translation.

The circuit above increases the output voltage by about 0.6V. This translates the 3.3V CMOS output voltage right into the 5V CMOS input range. The same amount of translation is done for the logic low voltage signal. However, the VIL (max) of the CMOS input is about 1.5V, so the voltage translated signal still meets the VIL parameter. There are a few things to consider for this configuration. When the 3.3V device outputs a logic 0, the circuit will also draw more current. So the limitations of the 3.3V device VOL specification on the circuit sink current should be carefully studied. In general, the higher the sink current, the higher the VIL. So be careful not to violate the VIL parameter. If the CMOS output VOL is too high, you must consider increasing the pull-up resistor value. If the resistor is too large, the diode bias current will be low, resulting in a slower switching rate for the diode.

Microchip新推出的16位PIC24系列单片机提供了可简化5V接口的独特功能。该系列单片机的输入引脚可承受 5V(或 5.5V)电压，即使器件正常情况下运行在3.3V或更低的Vdd电压下。这些输入引脚不需要连接到Vdd的箝位二极管，而是采用了不同的ESD保护机制。对于5V接口来说，这是非常重要的特性，因为这样不需要电阻分压器就可以直接将5V输出连接到3.3V器件。让我们回到图3的例子，可见添加了这一功能即可实现无缝的5V接口。

Some microcontroller products take this feature a step further by providing the ability to generate 5V outputs via external 5V pull-up resistors. 3.3V devices drive 3.3V outputs but tolerate 5V inputs. These pins provide digitally controlled open-drain outputs, giving you the option of pulling the pin up to 5V without violating any specifications. This feature allows for easy interfacing with 5V devices via CMOS inputs.

When using a pull-up resistor configuration (see Figure 6), the connection capacitance between the two devices needs to be considered to determine the rise/fall rate (and maximum switching frequency) of the signal at the port pin, and the applicable resistor value. Consider the following formula:

Where τ = RC time constant, R×C

PVdd = peripheral voltage Vdd

PVih(min) = Vih(min) value of the peripheral

If the following typical values ​​are used:

Pull-up resistor R = 1K

Capacitance C (due to pin and PCB capacitance) = 10pF

PVdd = 5V

PVih(min) = 0.7×Vdd = 3.5V

Then the rise/fall time ≈ 12nS

If the acceptable minimum rise/fall pulse time width is 50nS, then the maximum output frequency is 20MHz, which is sufficient for most peripheral interconnects.

One disadvantage of this approach is that when the MCU drives a logic low, additional current is consumed through the pull-up resistor. Therefore, when designing, you need to consider the speed and current size of the two factors to choose a compromise pull-up resistor. You need to choose a compromise resistor value for your application to provide the required speed and ensure that the current consumed does not exceed the specification.

Some may think that you cannot drive low impedance loads with this type of configuration. What if you want to drive a 5V relay? Fortunately, the above features also help when driving low impedance loads such as relays. Take a look at the circuit configuration in Figure 7. To drive this type of load, you need to define the pin as an output and drive it low. Here, the only limiting factor is the current sinking capability of the device. To turn off the load, define the pin as an input. Turning off the load will feed 5V directly into the input pin. Since the pin can withstand 5V, this is the correct action. In other words, you need to keep the output latch at logic low and turn the load on/off by switching TRIS (input/output control register).

This article has shown effective methods for bridging circuits powered by 5V and 3.3V. These methods are well matched to low-cost smart solutions for bridging circuits powered by different voltages during the conversion phase. At the same time, it is likely that most devices will soon move to lower power supplies, eliminating the need for circuit bridging. The methods presented in this article will certainly help to take advantage of the latest trends in the semiconductor industry and reduce system costs.