Power Supply Design Tips: Maximizing Power Supply Efficiency

The next step is to take the simple expression above and put it into the efficiency equation:

In this way, the efficiency of the output current is optimized (the specific demonstration is left to the students). This optimization can produce an interesting result.

The efficiency is maximized when the output current is equal to the following expression.

The first thing to note is that the a1 term has no effect on the current at which efficiency is maximized. This is because it is related to losses that are proportional to the output current such as the diode junction. Therefore, as the output current increases, these losses and output power increase and have no effect on efficiency. The second thing to note is that the best efficiency occurs at a point where the fixed and conduction losses are equal. This means that by controlling the components that set the values ​​of a0 and a2, the best efficiency can be achieved. Again, the effort is to reduce the value of a1 and increase efficiency. The result of controlling this term is the same for all load currents, so there is no best efficiency like the other terms. The goal of the a1 term is to minimize while controlling cost.

Table 1 summarizes the various power loss terms and their associated loss factors, which provides some trade-offs for optimizing power efficiency. For example, the choice of the power MOSFET on-resistance affects its gate drive requirements as well as Coss losses and potential snubber losses. Low on-resistance means that gate drive, Coss, and snubber losses increase inversely. Therefore, you can control a0 and a2 by choosing the MOSFET.

Table 1 Loss coefficient and corresponding power loss

Substituting the optimum current back into the efficiency equation algebraically, we solve for the maximum efficiency:

The last two terms in this expression need to be minimized to optimize efficiency. The a1 term is simple and can be minimized. The last term can be partially optimized. If we assume that the Coss and gate drive power of a MOSFET are related to its area, and that its on-resistance is inversely proportional to its area, then the optimal area (and resistance) can be chosen for it. Figure 1 shows the results of the optimization for die area. When the die area is small, the on-resistance of the MOSFET becomes the efficiency limiter. As the die area increases, the drive and Coss losses increase and at some point become the dominant loss components. This minimum is relatively wide, giving the designer flexibility in controlling the cost of the MOSFET to achieve low losses. The lowest losses are achieved when the drive losses are equal to the conduction losses.

Figure 1 Adjusting MOSFET die area to minimize full-load power loss

Figure 2 is a plot of the efficiency of three possible designs around the sweet spot of Figure 1. The normal die area is shown for each of the three designs. At light loads, the efficiency of the larger die is compromised by the increasing drive losses, while at heavy loads the small device becomes overwhelmed by the high conduction losses. It is important to note that these curves represent a three-to-one change in die area and cost. The normal die area design is only slightly less efficient than the full power large area design, and is higher at light loads (where the design will often operate).

Figure 2: Peak efficiency occurs before full rated current