Benefits of using a boost follower in a power factor correction preregulator

Traditionally, PFC (power factor correction) offline power converters are designed with two power stages: The first power stage is usually a boost converter, because in this topology there is a continuous input current that can be varied using a multiplier and average current mode control to achieve a near unity power factor (PF). However, the boost converter requires a higher output voltage than the input and an additional converter to step the voltage down to a usable level (see Figure 1).

Figure 1 Functional block diagram of a two-stage power converter

A traditional boost converter has a fixed output voltage that is higher than the maximum peak line voltage. However, we do not have to regulate it because the step-down converter (2 power stages) regulates the variable. As long as the voltage step-up exceeds the peak input voltage, the converter will regulate properly. Using a boost follower to track the line voltage changes has many benefits, such as reduced boost inductor size and lower switching losses when the peak line voltage is lower.

Figure 2. How the output voltage of the boost follower and traditional PFC pre-regulator tracks Vin(t)

Boost inductor (L)

The choice of boost inductor is based on the maximum ripple current (ΔI) allowed at the lowest peak line voltage (Vin(min)) and the maximum duty cycle (D). The following equations are used to calculate the inductance in each type of pre-regulator power stage (conventional or follower). ΔI is 20% of the peak input current[5]; Pout is the maximum output power; and Vout (min) is the minimum boost output voltage. These equations show that the inductor in the boost-follower topology can be much smaller over a larger input voltage range.

For example, if you want to use the above equation to calculate the inductance of a boost follower topology in a 250W application with a wide input range of 85V to 265V, and the output voltage range is 206V to 390V, tracking the input voltage, you will need an inductor of 570μH. Under the same conditions, for a traditional 390V fixed DC output topology, you will need an inductor of 1mH.

Boost Switching Losses

The following equation calculates the power loss in the boost FET (PQ1) [3][5] and shows that the parasitic FET capacitance loss (PCOSS) and FET switching loss (PFET_TR) are much smaller in the boost follower PFC when the line voltage is low compared to the conventional PFC. This is because the output voltage (Vout(min)) is much smaller in the boost follower PFC when the line voltage is low, thus reducing the overall switching loss.

For example, the power loss of an IRFP450 HEXFET (same conditions applied to the boost inductor) is 11.5W in the boost follower, while the power loss in the conventional regulator is 19.5W, which means that the boost follower is about 3% more efficient at lower line voltages.

Figure 3 Comparison of laboratory results between boost follower PFC and traditional PFC

Boost FET Heatsink Size Reduction

The calculation of the boost FET heat sink size is performed at the lowest input voltage because the FET power loss is highest at this time. The following equation can be used to calculate the minimum thermal resistance of the heat sink (Rθsa) required for traditional or follower type. Where Tjmax is the maximum junction temperature, Tamb is the maximum ambient temperature, Rθjc is the thermal resistance from semiconductor junction to case, and Rθsc is the thermal impedance from heat sink to case.

From this equation we can see that due to the reduced FET power losses (P_semi) and increased thermal impedance, the required heat sink size is reduced - another benefit of the boost follower over the conventional topology. Using the power losses calculated in the boost switch losses section, we can select the heat sinks for the boost follower and conventional PFC pre-regulator to make this benefit of the boost follower more apparent. The design requirement for the conventional or follower topology is that Tjmax cannot exceed 75% of the maximum FET rated temperature, which Tamb maintains at 40°C with a fan at a linear speed of 150 ft/min. The IRFP450 used requires an AVVID heat sink part number 53002 (approximately 4.125 cubic inches) in the conventional topology and AVVID 531202 (approximately 1.38 cubic inches) in the boost follower topology - a reduction of approximately 66%.

Selection of holding capacitor

Unfortunately, you can't get more performance without increasing the cost. While you get the benefits, you also introduce some disadvantages into the circuit, including slower transient response and larger hold capacitors (Cboost). The following equation estimates the capacitor size required for the hold time (tholdup). Vholdup is the hold voltage required by the design.

Calculating the minimum required hold-up capacitance for the boost follower and conventional pre-regulators shows how high the capacitance can be in the boost follower topology. In a 250W application with a 16.7-ms hold-up time and an 85-V hold-up voltage, the minimum output voltage Vout (min) is 390V for the conventional topology and 206V for the boost follower topology. The hold-up capacitance required for the boost follower topology is approximately 330 μF, while the conventional converter topology requires only 150 μF.

in conclusion

Boost follower PFC pre-regulators offer many advantages over traditional PFC pre-regulators, and power supply designers are interested in these advantages. These advantages include higher efficiency at lower line voltages, smaller heat sinks for the boost switch, and smaller boost inductors to meet similar power supply requirements. Unfortunately, to gain the benefits of using a boost follower, designers face slower transient response and larger boost hold-up capacitors.