Design of LED drive circuit based on DC/DC converter

1 Introduction

LED has been widely used in lighting, backlight and other fields due to its advantages of low power consumption, high luminous efficiency and long service life. The brightness of LED is proportional to the working current. In order to maintain the stability of brightness, a stable constant current power supply is required. In terms of power management, DC/DC converter has the advantages of small size, low power consumption, high efficiency and easy use, so it is widely used. LED drive circuit based on DC/DC boost converter has also become a classic LED drive method. DC/DC converter has a variety of control modes, among which the peak current mode has been widely used in the industry due to its advantages such as faster response speed. However, when the duty cycle is greater than 50%, the circuit is prone to subharmonic oscillation, which needs to be eliminated by introducing a slope compensation circuit.

Section 2 of this paper introduces the specific implementation method of the circuit, Section 3 gives the simulation waveform of the circuit, and Section 4 summarizes the entire paper.

2 Circuit Design and Analysis

Figure 1 shows the LED driving circuit designed in this paper, which consists of four parts: ramp signal generating circuit, current sampling and superposition circuit, error amplifier, and PWM comparator.

Figure 1 LED drive circuit based on DC/DC converter

2.1 Ramp signal generation circuit

图2所示为斜坡信号产生电路，其中，OP为箝位运算放大器。可以看出，基准电压VREF经过电阻R10与R11分压后，再经运算放大器的电压箝位后作用于可调电阻RL上，产生一个恒定的电流。电流经过MP1~MP4四个MOS管的镜像后，成为对电容进行充电的恒定电流信号。由电路结构可以算出此电流的大小为：

Since the reference voltage is a constant voltage, the resistors R10 and R11 match each other, and the resistor RL is a resistor with a near zero temperature formed by a polycrystalline resistor with a positive temperature coefficient and a well resistor with a negative temperature coefficient in series, this current is approximately a reference current. The current acts on the capacitor, and the square wave signal controls the charging and discharging of the capacitor to generate a sawtooth voltage signal, and the slope m0 of the sawtooth wave is:

After the sawtooth voltage is raised by VEB1, it is input to the signal superposition module. The voltage at the VSLOPE terminal is a sawtooth voltage. Therefore, in Figure 2, the current mirror adopts a self-biased structure. Compared with the ordinary common source and common gate current mirror, this current mirror has a larger output voltage swing and can meet the requirement of a wide range of voltage variation at the VSLOPE terminal. ‖

Figure 2 Ramp signal generation circuit.

Compared with the voltage mode, the current mode has a faster transient response speed. However, when the duty cycle is greater than 50%, the circuit is prone to subharmonic oscillation, which requires an additional slope compensation circuit to overcome.

This paper adopts a compensation method in which the sampling circuit output signal is superimposed with the slope compensation signal.

The current sampling and superposition circuit is shown in Figure 3. The current sampling circuit is actually a two-stage operational amplifier. MN3 and MN4 are the first stage of the operational amplifier, forming a common-gate differential pair structure, and using current mirrors MP14 and MP15 as active loads. MN5 is the second stage of the operational amplifier, which is a common-source structure, and uses MP12 as an active load.

Figure 3 Current sampling and superposition circuit.

The role of MP1 is to provide a static current for the second stage, so that when the CS terminal is zero, the second stage can still have a static current to keep the second stage turned on. The specific principle is: if the size of MP14 and MP15 is the same, the currents I5 and I6 are equal; at the same time, the size of MN3 and MN4 is the same, and their gate-source voltages should also be the same. As can be seen from Figure 3, the gate potentials of MN3 and MN4 are the same, which determines that their source voltages should also be the same, that is, the voltage drops on resistors R4 and R5 are the same, so that currents I7 and I8 are equal. Since I7=I4+I5, I8=I3+I6, combined with the previous analysis of I5=I6, we can get I3=I4. From the above analysis, it can be seen that the current of the second stage of the op amp is set by MP13, and the size of the second stage static current is adjusted by changing the current mirror ratio of MP13 and MP16.

When the CS terminal has a value of VCS, the output of the first stage of the op amp should be increased, thereby increasing the current I3. The specific analysis is that since the size of I4 and I5 is constant, the voltage drop on the resistor R4 is constant. After the voltage on the CS terminal increases by VCS, the voltage on R4 also increases by VCS, and the voltage on R5 should also increase by VCS. This requires the current on R5 to increase by VCS/R5. Since I6 remains unchanged, I3 should increase by VCS/R5. VCS is the voltage drop caused by the inductor current acting on a small sampling resistor. The change of VCS reflects the change of the inductor current, and the change of VCS is completely proportional to the change of the inductor current. Assuming that the sampling resistor is RS and the slope of the inductor current is K, the slope of I3 is KRS/R5. Assuming that the rising slope and falling slope of the inductor current are K1 and K2 respectively, the corresponding slopes of I3 are K1RS/R5 and K2RS/R5 respectively. The current superposition module consists of MP10, MP11, R3 and Q3. As can be seen from Figure 2, VSLOPE is one VBE higher than the voltage on capacitor C1, and in Figure 3 it drops one VBE before acting on R2, which is equivalent to the voltage on capacitor C1 acting directly on resistor R2. Combined with formula (2), the slope m1 of current I2 is:

The current acts on the resistor R3 through the mirror image, and the compensation slope m can be obtained:

The current on MP11 is the sampling and amplifying current of the sampling circuit. This current acts on the resistor R3, and the slope m′ of this voltage can be obtained:

‖

The falling slope of the inductor current is converted into:

It can be seen from the literature [3]~[4] that in order to ensure that the circuit does not have subharmonic oscillation, m>1/2m′2 should be set, that is:

Subtracting R3 gives:

The compensated signal passes through Q3 to raise VBE, generating a RAMP signal, which is input to PWM and compared with the output of the error amplifier.

The function of the error amplifier is to sample the feedback voltage, output a control signal, and then input it into the PWM comparator to control the current peak value. When the LED is working, due to process deviation, the forward voltage drop on each LED will not be the same, so the voltage at each LED voltage sampling point will not be the same. In order to ensure that each LED can work normally, the circuit should sample the signal with the lowest voltage and input it into the error amplifier to compare it with the reference voltage. The error amplifier in this article has a self-selection function, and the circuit structure is shown in Figure 4.

Figure 4 Error amplifier.

Since the input pair of tubes is a PMOS tube, the bias current will flow to the path with the lowest gate voltage, and the other three paths with relatively high gate voltages will be turned off, ensuring that only one transistor at the inverting input end of the error amplifier is working when the circuit is working normally.

As can be seen from Figure 4, the circuit is a single-stage folded common source and common gate structure, which has a high output resistance and ensures a high voltage gain of the circuit. Combined with the basic knowledge of analog integrated circuits, the static gain of the circuit can be obtained:

Among them, gm is the transconductance of the input differential pair tube, // represents the parallel connection of resistors, gm14 and gm35 are the transconductances of transistors MN14 and MP35 respectively, ro1, ro14, ro35, ro30 are the output resistances of the differential input pair tube and MN14, MP35, MP30 respectively.

The error amplifier in this article has only one main pole, at the output of the amplifier, which is related to the resistance and capacitance of the output, and its size is represented by p:

Among them, C is the capacitance of the output terminal, which is mainly the parasitic capacitance of the transistor in the open-loop state.

2.4 PWM Comparator

The PWM comparator compares the current sampling signal after slope compensation with the control signal output by the error amplifier. When the peak signal output by the current sampling circuit reaches the value of the control signal, the PWM signal flips, generating a very narrow pulse signal, triggering the power tube to shut down. The PWM comparator designed in this paper is shown in Figure 5. Compared with the ordinary comparator, there is an additional transistor MP47 on the left side of the differential pair.

Figure 5 PWM comparator.

When the circuit starts, the output voltage of the system is very low, which will make the output signal of the error amplifier very high, causing the duty cycle of the gate drive signal to reach 100%, resulting in a very high pulse at the DC/DC output. After adding the SS terminal, the voltage signal at the SS terminal will rise slowly at startup, shielding the very high Vea control signal, causing the duty cycle of the gate drive signal to rise slowly, and realizing the soft start of the circuit. When the soft start is successful, the voltage at the SS terminal will also rise to a level higher than Vea, thereby shutting down the MP47 and the circuit enters a normal working state.

‖ 3.1 Error Amplifier Gain and Phase Curve

Figure 6 shows the gain and phase curves of the error amplifier, where Gain and Phase represent the gain and phase of the error amplifier in the open-loop state. It can be seen from the figure that in the open-loop state, the static gain of the error amplifier can reach 70dB, and the 3dB bandwidth can reach more than 10kHz; it can also be seen that the circuit has only one main pole, so there can be a 90° phase margin.

Figure 6. Gain and phase of the error amplifier.

3.2 Functional simulation of the overall circuit

Figure 7 shows the functional simulation results of the overall circuit. In the figure, OSC, SLOPE, CS, VEA, RAMP, and PWM represent the oscillator output signal, the ramp signal, the current sampling signal, the error amplifier output signal, the output signal after the sampling circuit output and the ramp signal are superimposed, and the output signal of the PWM comparator.

Figure 7. Simulation results of the overall circuit function.

As can be seen from Figure 7, the ramp signal generating circuit outputs a sawtooth wave signal SLOPE with a fixed slope under the control of the oscillator signal. This signal is superimposed with the signal output by the current sampling circuit to generate a RAMP signal. When the circuit is stable, the error amplifier output is a constant value. When the power tube is turned on, the inductor current continues to increase, the sampling current at the CS end increases synchronously, and the RAMP signal also increases synchronously. When the value of the RAMP signal reaches Vea, the PWM comparator will flip and output a pulse signal to turn off the power tube.

Then, the inductor current starts to decrease, and the sampling point current disappears until the next working cycle, when the clock signal output by the oscillator turns on the power tube again.

4 Conclusion

This paper designs an LED driving circuit based on DC/DC converter, including inductor current sampling circuit, ramp signal generating circuit, error amplifier and PWM comparator. The sampling circuit samples the current signal on the inductor, amplifies it and superimposes it with the slope compensation signal, and then outputs it to the PWM comparator, and outputs a voltage pulse under the control of the error amplifier output signal to control the shutdown of the power tube.

The slope compensation adopts the upper slope compensation method, the circuit structure is simple and easy to implement. The error amplifier has the function of automatic signal selection, and does not need to add a selector, which can greatly reduce power consumption and layout area.