Estimation of Available Device Power in Power over Ethernet Applications

Many existing Ethernet devices are migrating from wall adapter power to the new IEEE 802.3af Power over Ethernet (PoE) standard. In the past, power system efficiency was not a big issue with wall adapters, but this has changed with PoE. Applications where functional circuits begin to draw power in the 10W range require tight control of power usage.

Once the functions required by the 802.3af standard are performed, first, we will determine the net power available. Second, we will introduce a modeling method for common DC/DC converters, calculate the power available to the application circuit, and compare two topology examples. The modeling process allows designers to identify topology methods and technical issues before designing the initial circuit.

PoE Front-End Losses

Figure 1 shows the basic block diagram, showing the interconnection of the power supply equipment (PSE) to the application circuit through the DC/DC converter. The calculations yielded the results shown in Table 1, assuming that the PSE output (minimum 44V) is connected to the PD through a 20Ω cable. The PD front end has a transformer (1Ω total, 0.5Ω on each side of the center tap), a full-wave bridge, and a hot-swap controller (i.e., PD controller) with a series 1Ω switch (FET).

Table 1 PoE power distribution and front-end loss analysis

The maximum available power of the PD function circuit is 12.16 W. The cable loss specified by the 802.3af standard is 2.45 W in the worst case, and the input diode bridge determines the additional front-end loss of 0.78 W.

Figure 1, Basic PoE Block Diagram

Power Conversion Stage Modeling
Simple modeling techniques help designers understand the effects of different topologies and technology choices before committing to actual designs. Simple efficiency assumptions provide quick qualitative results, allowing topology comparisons and optimizations. The final results may not deviate much from the assumptions, so designers should always specify the available power lower than the above results, leaving some margin.
First, let's take a look at the baseline of a single-stage converter to an output voltage. A 3.3V single output converter with 90% efficiency will produce 0.9×12.16 = 10.9W of available output power. Although 90% efficiency may be optimistic, it does provide a baseline for comparison with other topologies.
Next, we will estimate the output power provided by a more complex power supply. We use simple modeling techniques to study how each regulator topology and technology affects the output power. We assume that the output voltages are +5V, 3.3V, 2.5V, and 1.8V at currents of 0.2A, 2A, 0.25A, and 0.25A, respectively. This adds up to a reasonable power of 9.6W.
Figure 2 shows two possible power architecture and technology choices. Topology 1 illustrates the adaptation of an existing equipment design, with its 12V wall adapter replaced with a 48V to 12V front end. Topology 2 attempts to maximize the available power.

Figure 2, Two Power Topology Options

To evaluate the model, we start with the rightmost regulator, calculate its losses and total input power, and then use these results to evaluate the next regulator to its left. For simplicity, we assume that the switching efficiency is 90% and that the linear regulator has no bias current. The calculation results for each regulator type are summarized below.
Definitions
IOUT = Applied load current
PIN_Next_Stage = Power drawn by downstream converter or linear regulator
Linear regulator stage
POUT = (VOUT × IOUT) + PIN_Next_Stage
PIN = VIN × POUT / VOUT
PLoss = PIN -
POUTSwitching regulator stage
POUT = (VOUT × IOUT) + PIN_Next_Stage
PIN = POUT / Effiviency
PLoss = PIN -

POUTTable 2, Topology 1 Model

Using the data in Table 2, we perform calculations for the Topology 1 model shown in Figure 2. Let’s look at the data for the lower portion of Chain 1 in Table 2, starting with the input power and losses for the 1.8V regulator; notice that there is no power for the next stage. The calculations for the 2.5V regulator are similar, where the output power consists of 0.25A times 2.5V to the load, plus the previously calculated input power for the 1.8V regulator. The input power for the 3.3V switching regulator is the total output power divided by the efficiency of that stage (0.9%). The power dissipated by the 3.3V regulator is again the input power minus the output power. The calculation for the upper portion is similar to the Chain 2 data. The parameters for the 48V to 12V regulator are similar to the calculations for the 3.3V regulator, where the total output power is the sum of the upper and lower input powers. To get a feel for the performance of this topology, we add the losses for each section together, and the apparent efficiency is calculated as follows:
Efficiency = 1 – Total-Losses/Input-Power
The output power available in Table 2 is the input power minus all the calculated losses for each section.
The input power for Topology 1 exceeds the available amount. To give more interesting results, the 3.3V load shown is adjusted until the input power is 12.16W. The bold values ​​in Table 2 reflect the case where the 3.3V supply load is reduced from 2A to 1.83A.
Topology 2 is modeled in a similar manner to Topology 1 using the data in Table 3, but with a slight difference. A fictitious 3.3V regulator is modeled with an efficiency of 1 to give the correct totals for power and losses.

Table 3, Topology 2 Model

The 90% efficiency used for the 48V to 3.3V converter in Topology 2 is quite optimistic for a real synchronous output rectifier circuit.
Conclusion
After accounting for the 802.3af standard capabilities, 12.16W is the maximum power available to other electronic devices, including regulator losses.
The impact of topology and technology selection for PoE applications is quite dramatic. Topology 1 delivers only 8.11W to the application circuit, while Topology 2 delivers 10.43W, a 28% improvement. If the baseline single-output converter is 10.9W, then all three additional outputs in Topology 2 only consume 0.47W! The 3.3V converter uses a diode output converter (85% efficiency) instead of a synchronous rectifier, which reduces the available power by 0.61W.
This modeling technique allows designers to quickly calculate the available output power based on topology and technology selection, and use this information to make a comprehensive trade-off between available power, complexity, and cost.