AD9913's high sensitivity and low power consumption benefit power-saving designs

Direct digital frequency synthesis (DDS) has fast frequency switching and modulation capabilities and is widely used. However, when low power consumption and low cost are the main considerations, DDS often has to take a back seat to analog phase-locked loops (PLLs). The AD9913 changes this situation, not only providing the fast switching and modulation flexibility of DDS technology within a 125MHz output bandwidth, but also having low power consumption characteristics similar to PLLs, with a power consumption of only about 50mW.

The power consumption of DDS solutions has always been relatively high. For example, the AD9850, one of the first DDS products launched in the mid-1990s, integrated a digital-to-analog converter (DAC) and consumed 380mW at a 50MHz output bandwidth. The AD9913 uses innovative technology to improve its bandwidth-to-power ratio by 20 times compared to the AD9850.

The benefits that the AD9913 brings to portable and/or instrumentation applications are threefold: low power consumption of 50 mW enables handheld and other portable applications to benefit from DDS technology; the programmable analog-to-digital architecture is an attractive feature for network clock and instrumentation applications, and it supports the synthesis of frequencies that are any rational fractions (ratios of two integers) of the same rate. Traditional DDS can only synthesize rational fraction frequencies of the same rate whose denominator is a power of 2, such as 1/4 and 5/16, while the AD9913 is not limited by "powers of 2" and can generate any rational fraction frequencies of the same rate, such as 1/10, 3/7, or 286/11487, as long as they are within the programming range of the AD9913; finally, the AD9913, like some of ADI's earlier DDS products, is extremely flexible in generating a variety of waveforms.

The AD9913 achieves its low power consumption by incorporating several innovative power-saving techniques. The first innovation involves the phase-to-amplitude conversion portion of the DDS, which converts the instantaneous phase value produced by the phase accumulator into an amplitude value based on a sine and/or cosine function. Traditionally, this task has been performed by a read-only memory (ROM) lookup table. However, as DDS technology has continued to increase in speed and complexity, the power burden of the ROM approach has become unacceptable, requiring the use of a proprietary angle-rotation algorithm that relies on a computational engine to perform the sine and/or cosine conversion. The angle-rotation algorithm approach dates back to the AD9850 and significantly reduces power consumption compared to the ROM lookup table approach. Without the angle-rotation algorithm, many early DDS products would have required special heat-sinking packages to accommodate the higher power consumption. In addition, heat dissipation considerations may have forced us to subtract many useful features from existing DDS products, such as digital phase and/or frequency modulation of the DDS output signal, digital filtering to reduce sin(x)/x losses, and the use of multiple DDS cores for multichannel applications.

The second major power-saving breakthrough can be attributed to Analog Devices’ patented phase-interleaved DDS architecture (U.S. Patent No. 6,587,863). The power savings achieved by the phase-rotation algorithm made it possible to consider running multiple DDS cores on the same chip. We found that running multiple DDS cores at lower sample rates consumes less power than running one DDS core at a very high sample rate, which is a very significant breakthrough because innovations in DDS technology are necessary to fully exploit the new high-resolution (14-bit or higher), high-sample rate (1 GHz or higher) digital-to-analog converter (DAC) cores. The interleaved DDS architecture enables designers to integrate multiple already power-reduced DDS cores and run them at a lower sample rate than the higher-frequency DAC cores. This innovative architecture, along with the adoption of the 180nm CMOS manufacturing process, results in a significant increase in DDS output bandwidth with only a slight increase in power consumption over the previous generation of low-frequency DDS products.

However, even with these innovations, power consumption is still too high for handheld and portable applications. To address this problem, another innovation is needed. To this end, we have improved the angle-rotation algorithm and introduced a new proprietary algorithm to further reduce the power consumption of the DDS core. The new algorithm, combined with design principles that focus on low-power operation, allows designers to achieve the desired low-power design goals. The new design principles include turning off any unnecessary internal clocks that are not required for a specific operating mode and reducing the power consumption of each circuit block without degrading spectral performance or unduly limiting bandwidth.

The result of these innovations is the AD9913, which can sample at rates up to 250MHz while consuming only 50mW of power. At a 250MHz sample rate, the available bandwidth is approximately 100MHz. The output frequency capability and low power consumption of the AD9913 make it ideal for a variety of radio control units, as well as wireless scanners for bar codes and radio frequency identification (RFID) tags. However, for applications requiring bandwidths above 100MHz, an auxiliary PLL must be used for upconversion. Other handheld/portable applications that can benefit from low-power DDS technology include software-defined radios (SDRs), remote or portable cable TV test equipment, medical blood glucose meters, wireless fire alarms, and electronic measurement equipment such as spectrum analyzers and waveform generators.

Figure 1 shows the low power consumption of the AD9913 at a nominal output frequency of 100MHz. The curves in the figure correspond to three different operating modes (single tone, linear sweep, and programmable modulus) and two REFCLK input drive methods (directly driven by a differential source or directly driven by a single-ended source with the internal PLL disabled).

Figure 1 Relationship between power consumption and sampling rate of AD9913

The AD9913 is different from traditional DDS devices in its unique programmable analog-to-digital architecture. Traditional DDS relies on a phase accumulator to resolve frequencies, and the size (number of bits) of the accumulator determines the frequency resolution of the DDS.

If the phase accumulator has a C-bit resolution, the frequency resolution provided by the traditional DDS is fS/2C, where fS is the sampling rate of the DDS. The digital tuning word M can be any integer from 0 to 2(C-1). In theory, the allowable tuning word range is from 2(C-1)/2C-1, but this will result in the synthesis of the Nyquist image frequency (i.e., the counter rotating phasor). The familiar DDS frequency synthesis equation can be listed based on the digital tuning word and the DDS sampling rate (fS), where fO is the DDS output frequency:

fO/fS=M/2C (1)

Because M must be an integer, a traditional DDS can only synthesize 2(C-1) unique frequencies for a given sampling rate. That is, when M=0, the output frequency is 0 (DC); when M=2(C-1)-1, the output frequencies differ by only 0.5fS. All remaining output frequencies are increments of fs/(2C), the frequency resolution of the DDS. In most cases, such fine frequency resolution is more than satisfactory. For example, the AD9913 has a 32-bit accumulator with a frequency resolution of (250MHz)/232, or about 0.058Hz.

Now consider a case where a traditional DDS has a 32-bit accumulator that is required to synthesize an output frequency that is exactly 1/1000 of the sampling rate. This means fO/fS = 1/1000, which can be substituted into the left side of Equation 1 and solved for M to obtain: M = 232/1000, or M = 4294967.296. This M is obviously not an integer, but the traditional DDS requires that M must be an integer value, so its closest integer value is used, which is 4294967 in this case. The problem is that using this tuning word, you cannot synthesize a frequency of exactly 0.001fS, but rather a frequency of approximately 0.000999999931fS. In some applications, such as network clock applications, this slight deviation is unacceptable.

The C-bit phase accumulator in a traditional DDS results in a fixed modulus (N), that is, N=2C. The programmable modulus DDS architecture makes a clever modification to the phase accumulator so that the modulus can be any integer that satisfies the condition 1≤N≤2C. In other words, the value of N can be set by the user. For the programmable modulus DDS architecture, when N=1 or N=2, the synthesized frequency is 0Hz, so the minimum available modulus (for generating outputs other than DC) is N=3. Like traditional DDS, the programmable modulus DDS also requires that M in equation 1 is an integer. However, since N is programmable, the DDS output frequency equation becomes

fO/fS =M/N (2)

Equation 2 may seem mundane at first glance, but it actually has a lot of meaning. Consider the case where a particular modulus N=2C is chosen. In this case, the set of frequencies that can be synthesized is the same as that of a traditional DDS. However, a programmable modulus DDS includes not only the entire set of frequencies of a traditional DDS, but also many more. This is because each specific value of N (from 3 to 2C) corresponds to all frequencies associated with M (1≤M<0.5N-1). For any given sampling rate, the set of possible output frequencies it represents is much larger than that of a traditional DDS.

The advantage of the programmable analog-to-digital architecture is that almost all rational frequency ratios can be synthesized. For example, if M=1 and N=1000, the frequency of fO=fS/1000 can be accurately synthesized. In fact, not only can fO=fS/1000 be synthesized, but also the harmonics of fS/1000 (up to 499, that is, the highest harmonic order is 0.5N-1).

Maintaining low power while developing a programmable modulus is no small feat. It may seem simple, just add some extra logic to modify the traditional accumulator to force it to roll over at the new modulus value, but remember that the original DDS power-saving innovation involved an angle-rotation algorithm that was designed to operate efficiently when the accumulator modulus was a power of 2. When the accumulator modulus changes to a value other than a power of 2, the power-saving angle-rotation algorithm cannot be used.

The cleverness of the accumulator improvement is reflected in two aspects. First, it allows the modulus to change while still meeting the "power of 2" requirement of the angle-rotation algorithm. Second, it achieves the first point while minimizing the impact on spurious performance. In Figures 2 and 3, the spectrum analyzer sweep frequency range is 0 to 125MHz, and the AD9913 operates at a sampling rate of 250MHz. In Figure 2, the AD9913 is configured as a traditional DDS with a frequency tuning word of 262160001 (f0≈15.26MHz), which is the closest value to M/N=1000/16383 that a traditional DDS can achieve. Figure 3 uses a programmable modulus setting. The frequency difference between the two cases is only about 0.00136Hz (about 1MHz). Except for slightly different spurious components, the two traces look almost exactly the same.

Figure 2 Tuning limitations of standard DDS technology

Figure 3 AD9913 programmable module tuning capability

Despite its very low power consumption, the AD9913 does not compromise waveform generation capabilities and is still capable of generating waveforms where linear frequency or phase changes in a ramped form over time. The user sets the start and end points (32 bits for frequency and 14 bits for phase). The step size and step rate parameters for both ramp directions (from start to end and from end to start) are independently programmable. Using these control parameters and other user-controlled features, a wide variety of modulated output signals can be generated. An example of the waveform generation capability is shown in Figure 4, showing a time domain plot of a frequency sweep from 1MHz to 10MHz in 6μs (6kHz steps, 4ns intervals). The rising edge of the lower trace indicates the start of the frequency sweep. After reaching 10MHz, the device folds back and holds 1MHz, so the trace clearly shows the end of the frequency sweep.

Figure 4 Time domain waveform generated by ADS9913 frequency sweep

The AD9913 also integrates a reference clock multiplier, allowing designers to use lower frequency clock sources. In addition to directly using a high frequency clock source to drive the device, designers can also use a low frequency clock source or crystal resonator with the AD9913 integrated PLL (1X to 64X) frequency multiplier to generate the required 250 MHz internal sampling clock. When sampling a direct clock signal, the reference clock (REFCLK) input port of the AD9913 accepts a differential or single-ended signal source.