How to keep component costs low for high-performance mobile CPU power supplies

New processors in laptops place higher demands on power supplies: higher current, faster response to load steps, and faster adjustment of output voltage after the voltage identification (VID) code is updated. If an existing power supply design can meet the latest load step response specifications, guarantee low ripple, and achieve high efficiency in all operating modes (especially standby mode), then reusing the design into a new system is a preferred option. Unfortunately, older controllers cannot provide fast load step response directly with the existing output inductor, so they require additional large capacitors to smooth the transient process. However, the space available for new power supply designs is the same as that of older designs, so additional capacitors cannot be placed. This article will discuss a possible alternative.

A new controller to solve a new problem

For most notebook applications, a two-phase design can keep the inductor current at 20A per phase or less for the fastest response to load steps and the lowest cost. The switching frequency must be set high enough to respond to load transients at the required slew rate. The MOSFET RDSON must be low to minimize high-frequency switching losses, and the controller feedback loop bandwidth must be high enough to ensure fast response. Unfortunately, older controllers have limited bandwidth. Increasing the switching frequency does not help because the narrow bandwidth limits the loop response. The inductor cannot provide large current steps, so more bulk capacitors are required. The cost and size of this design are very high, and it limits the real-time output voltage step response.

New multiphase synchronous controllers can address these issues. Their stable and high-speed feedback loops enable smaller, lower-cost designs. Some controllers also support single-phase operation at lower switching frequencies, greatly improving efficiency at low and intermittent current conditions.

When properly compensated, high-bandwidth controllers can handle the largest load steps without oscillation. The controller can source more current through the inductor, thereby taking less charge from the bulk capacitor. New controllers can respond quickly to current transients and conduct multiple phases simultaneously, increasing available load current without adding bulk capacitors. Controllers that can handle large load steps make the selection of inductors, capacitors, and MOSFETs simple.

Determining the Inductance Value

Switching frequencies of several hundred kHz per phase ensure a good balance between switching losses, ripple, and size of the output filter. The inductor value in the output filter is determined by the ripple requirement rather than the output voltage.

Where R0 is the load resistance and Vripple is the permissible ripple voltage caused by the inductor ripple current. The peak-to-peak value of the ripple current in the inductor should be less than half of its maximum DC current. The ripple voltage corresponding to 8A ripple current with a load of 2.5mΩ is 20mVpp. For a two-phase power supply, the Vvid output voltage is 1.115V, FSW=280kHz, and L≥423nH can be calculated from formula (2).

The inductor should not saturate at the peak current per phase and should be able to withstand the core losses and average winding current. Using the smallest possible inductor can reduce the number of output capacitors. The DC resistance of the inductor affects the current sensitivity in many controller designs, so a compromise needs to be made between power loss and measurement accuracy.

Minimize output capacitance value

Ceramic capacitors and bulk capacitors at the output of a switching regulator have different roles. Ceramic capacitors handle the high-frequency transients of the CPU, and placing them inside the CPU socket provides the best transient suppression, but this limits the number of capacitors that can be placed. If additional capacitors are needed, they must be placed close to the CPU socket.

The worst transient is usually the largest load step that occurs in deep sleep. The switch on-time, maximum output current step, and maximum output slew rate determine the design of the output filter at the CPU power pin. For most notebook applications, the output capacitance is at least 300μF, which can be obtained by 32 0805 10μF ceramic capacitors in parallel. Variations in parasitic parameters on the PCB will cause changes in the number of capacitors required.

Simply placing a bunch of large capacitors at the low-frequency output filter end has no benefits other than high cost and large size. Real-time voltage changes set an upper limit, that is, the power supply must be able to produce a voltage jump and settle to a specific error band within a given time. The output end also requires the output capacitor to have a minimum capacitance limit to ensure a smooth load voltage under the maximum load step Io condition and within the maximum tolerable overshoot range.

Under the condition of maximum tolerable overvoltage Vosmax, the load voltage is

Vo=Io×Ro+Vosmax

These equations determine the limiting value of the bulk capacitor Cx,

Where K=-ln (VERR / VV).

To satisfy the above equation, the equivalent series resistance (ESR) of the large capacitor should be less than twice the drop resistor Ro. If the solution to the above equation shows that Cxmin is greater than Cxmax, the inductor value can be reduced or more phases can be added to meet the Vvid step requirement. If the requirement is to maintain the same output ripple while reducing the inductor, the switching frequency should be increased.

For example, if Cz = 320μF, the real-time VID step is 22μs, 220mV step (tv and Vv), the overshoot voltage is limited to 27mV, and the steady-state voltage error (Verr) is 10mV, then the large capacitor should be in the range of 1.1mF to 2.1mF. If four 330μF aluminum electrolytic capacitors are used, and the typical ESR value of each capacitor is 6mΩ, the total capacitance value is 1.32mF and the total ESR is 1.5mΩ.

The equivalent series inductance (ESL) of the bulk capacitor should be low enough to suppress high-frequency ringing when a load step occurs.

ESL=Cz×Ro2×Q2, where Q2 is limited to 2 for a critically damped system.

If the ESL of the large capacitor is too large, you can increase the number of ceramic capacitors or use a large capacitor with smaller ESL.

MOSFET selection

MOS power devices in step-down power supplies need to have very low RDSON to minimize conduction losses and power dissipation. They also require very low input capacitance to minimize the on-time. Faster devices with lower CISS have higher RDSON, so a compromise needs to be made between these indicators. Due to the use of MOSFET drive circuits, the gate drive voltage is limited to 5V, so MOSFETs with logic level thresholds become the only choice. Power dissipation from the main current and ripple current is the main component of synchronous MOSFET power loss.

If the reverse transfer capacitance couples enough charge to the gate when the switch node goes high, the synchronous MOSFET may turn on unexpectedly. This can cause a shoot-through phenomenon where both the master and synchronous devices are turned on at the same time. To prevent this, use a feedback capacitor with a ratio of 1:10 or less to the input capacitance on the synchronous device.

The turn-off time of the synchronous MOSFET should be less than the non-overlapping dead time of the MOSFET driver for each phase. For example, the output impedance of the ADP3419 MOSFET driver from Analog Devices is 1.5Ω, and its typical dead time is 45ns. If a MOSFET with a typical gate resistance of 1Ω is used and the RC time constant is less than 45ns, the upper limit of the total gate capacitance value is 9,000pF. When using two parallel MOSFETs, each gate capacitance should be less than 4,500pF.

The high-voltage MOSFETs are required to withstand the power dissipation caused by the on-state current and switching losses. The switching losses come from the turn-on and turn-off of the switch, so the input capacitance of these FETs must be smaller than the input capacitance of the synchronous MOSFETs.

Another issue that needs attention is the loss of each phase driver circuit. The total standby power consumption of each driver plus the corresponding power consumption when providing gate charge should be less than the thermal dissipation limit of the driver at the maximum ambient temperature. For an SOIC package operating on a PCB with a temperature as high as 90oC, a total dissipation of 0.5W corresponds to a junction temperature of 120oC.

Recommended input capacitor values

The drain current of the MOSFET on the high-power side is approximately a square wave, with a duty cycle equal to n×Vout / Vin, and the maximum output current amplitude is multiplied by 1/n. In order to filter the input ripple, the ESR of the input capacitor must be very low, and the specific value is determined by the maximum RMS current. This RMS current is

Under the condition of minimum 8V battery voltage, when the maximum duty cycle Dmax is 0.144, it can be concluded from equation (5) that Icrms is equal to 9.05A.

The current rating given by the capacitor manufacturer may be based on a 2,000-hour service life, so a capacitor value with a rating higher than that using the calculated Icrms must be used.

The input capacitor value is determined by the amount of acceptable ripple. The capacitor's ESR and AC current must be low to meet system requirements.

Response to rapid load changes

The controller must respond effectively to the largest load steps and load releases. The old architecture with very long turn-on delays for each phase is not fast enough, and the controller, driver, and MOSFET must also respond fast enough to meet the requirements of real-time VVID changes.

Older single-edge designs wait until the next clock cycle to respond to load transients that occur when the controller is not operating. They can only clock one phase at a time, forcing the power supply to draw current from large capacitors.

Newer controllers use asynchronous correction to reduce load step response time and reduce the number of capacitors. They can turn on all phases immediately to provide current to the CPU without causing delays in the internal clock.

Synchronous buck controllers, such as ADI's ADP3207A, can respond to sudden load changes. They can turn on all phases in sync with the load step, providing maximum current without waiting. Their full-phase response time to a worst-case step is typically 1 μs or less. After the initial load step demand is met, the load can be supplied with additional current, and then the system enters normal operation, so the amount of ripple does not increase.

To handle large load steps, some controllers turn on all phases simultaneously. Most of them use a linear transfer function characteristic to eliminate the effects of load changes and control the output. However, the ADP3207A uses nonlinear gain to respond to load steps. The large signal of the largest load step puts the system transfer characteristic in the high gain section of the transfer function, causing all output phases to turn on. Smaller load steps correspond to the low gain portion of the transfer function curve, allowing each phase output to be independently adjusted using standard PWM methods. The benefits of this are better noise immunity and lower jitter because most of the noise will act on the small signal, low gain portion of the transfer function. Controllers with constant high gain are more susceptible to noise.

Most mobile applications require a two-phase power supply, but these controllers can be easily configured to support three-phase power operation for higher efficiency. The input current per phase decreases as the number of phases increases, so the current draw from the battery in a given time is also reduced, of course at the expense of additional components, which increases cost and space.

Figure 1: The ADP3207A and ADP3419 response to a load step when using a two-phase supply.

Figure 1 shows the response when a load step occurs and all phases are on. In this example, a two-phase supply is used.

Mobile controllers need to operate efficiently in low-power modes to save battery. The ADP3207A can switch to single-phase operation when the processor selects low-power operation. In this mode, the switching frequency is proportional to the load current to ensure optimal power efficiency. In addition, the single-phase synchronous MOSFET needs to be controlled to avoid reverse inductor current. Figure 2 shows a circuit example of the ADP3207A.

Figure 2: The ADP3207A can switch to single-phase operation when the processor selects low-power operation.

Conclusion

Controllers used in mobile applications are struggling to keep up with the latest changes in the demands of new mobile processors. By introducing new technologies to improve the response characteristics of the controller, the overall size and cost of the power supply can be maintained while reducing the response time, allowing newer high-performance mobile designs to be realized without affecting the overall size of the mobile PC and the cost to the end user.