MOSFET dual-chip power package simplifies power supply design

One of the main challenges facing power engineers today is that as commercial electronic products continue to shrink in size with increasing functionality, there is less and less space left for power circuits. One way to address this challenge is to take advantage of advances in MOSFET technology and packaging. By using higher performance MOSFETs in smaller packages, there is a trend in the industry to move from standard leaded packages such as the SO-8 to power packages with bottom-side drain pads. For high-current applications, power 6mm x 5mm packages such as the PowerPAK® SO-8 are common. But for lower current applications, the trend is to move to 3mm x 3mm power packages such as the PowerPAK 1212-8. In these packages, the RDS(on) is low enough to make these chips widely used in 10A DC-DC applications in notebook computers.

While 3mm x 3mm power packages have enabled a significant reduction in the space used by DC-DC circuits, there is an opportunity to reduce the space used even further and increase power density. One way to achieve this is to replace discrete monolithic MOSFETs with a package that combines two devices. SO-8 dual-die power MOSFETs have been available for a long time, but they are typically only able to handle load currents under 5A, which is perfectly fine for the 5V and 3.3V rails in netbooks and notebooks, but is clearly too low for systems with load currents of 10A or more.

That is why manufacturers strive to design dual-die power packages for MOSFETs, as this greatly increases the maximum current possible and provides better thermal performance than conventional surface-mount packages. By using the basic principle of this power package, which is to put two separate chips into one package, this device can reduce the area required for the power circuit.

PowerPAIR is one such package type. This package has a smaller form factor than the single-chip power 6 x 5 package (PowerPAK SO-8) and can reach a maximum current of 15A. In a notebook computer, two power 6 x 5 packages are generally used for such a large load current. The area occupied by the wires and the label area, as well as the location of the two devices, exceeds 60mm2. The size of this dual-chip power package is 6.0mm x 3.7mm, and the area occupied on the circuit board is 22mm2. Reducing the board space by 63% is very helpful to power engineers, because they have less and less space to design power circuits. It is impossible to achieve such a great benefit with the traditional SO-8 dual-chip power package.

Compared with two 6 x 5 power packages or two SO-8 packages, this device not only saves space, but also simplifies the design, and saves more space than two 3 x 3 power packages. The dual-chip power package can easily replace two 3x3 packages with one device, and even save space for wiring and marking on the PCB, as shown in Figure 1. Therefore, for 5A~15A DC-DC applications, using this device is a reasonable design step and one of the ways to increase power density.

The PowerPAIR dual-chip power package uses an asymmetric structure similar to a DC-DC buck converter, allowing optimized high-side and low-side devices to occupy the same package. As shown in Figure 2, the on-resistance of the low-side MOSFET is lower than that of the high-side MOSFET, which results in inconsistent pad area sizes.

Figure 2

In fact, the on-resistance of the low-side MOSFET is a critical characteristic of the device. Even with smaller packages, it is possible to reduce RDS(on) to less than 5mΩ at voltages up to 4.5V. This helps improve efficiency at maximum load conditions and also allows the device to run cooler, even in a small package.

Another benefit of this device is the layout. As you can see in Figure 2, the pinout of the package makes it easy to integrate into a buck converter design. What is even more special is that the input of the device is on one side and the output is on the other. Pins 2 and 3 correspond to VIN of the DC-DC circuit and are the drain of the high-side MOSFET. The small pad is also the drain pad of the high-side component. The larger pad is the larger pad for the switching node of the circuit, where the source of the high-side MOSFET and the drain of the low-side MOSFET are connected internally to the device. This node will be connected to the inductor. Finally, ground is pins 4 and 5, which are the source of the low-side MOSFET. Pins 1 and 6 are connected to the gate of the high-side and low-side MOSFETs respectively. This layout is simple and reduces the chance of wiring errors when using two devices. This layout also reduces the parasitic inductance associated with additional PCB traces required when combining multiple devices together:

A final benefit of moving to a smaller form factor dual-die power package is the efficiencies that can be achieved, which can help increase power density. The device was mounted on a single-phase buck converter evaluation board under the following conditions.

VIN = 12 V, VOUT = 1.05 V, VDRIVE = 5.0V, fsw = 300 kHz, IOUT max. = 15 A

The efficiency is measured over the entire power range. At 15A, the efficiency is 87% with the device case temperature just below 70 °C. The peak efficiency is above 91.5%. This performance helps reduce power losses and save energy in medical systems while also enabling small form factor designs.

Figure 3

The dual-die asymmetric power package in a 6.0mm x 3.7mm form factor is a significant advancement in MOSFET packaging technology. This package enables engineers to improve the performance of power supplies, reduce size, and simplify design while achieving the high efficiency or performance required by today's consumer electronics products.