Ultra-High-Speed ​​ADC

Using time-interleaved analog-to-digital converters (ADCs) to acquire synchronously sampled analog signals at a rate of billions of times per second is a great technical challenge for design engineers and requires very sophisticated mixed-signal circuits. The fundamental goal of time-interleaving is to double the sampling frequency by adding converters without sacrificing resolution and dynamic performance.

This article discusses the main technical challenges of time-interleaved analog-to-digital converters and provides practical system design guidance, including innovative component functions and design methods that can solve the above problems. This article also provides FFT results measured from a 7Gsps dual converter chip "interleaved solution". Finally, the article describes the application support circuits required to achieve high performance, including clock sources and driver amplifiers.

Increasing demand for higher sampling speeds

When and why would it be beneficial to increase the sampling frequency? There are multiple answers to this question. The sampling speed of the analog-to-digital converter basically directly determines the instantaneous bandwidth that can be digitized in one sampling instant. The Nyquist and Shannon sampling theorems prove that the maximum available sampling bandwidth (BW) is equal to half the sampling frequency Fs.

A 3GSPS analog-to-digital converter enables the acquisition of a 1.5GHz analog signal spectrum in one sampling period. If the sampling rate is doubled, the Nyquist bandwidth is also doubled to 3GHz. Doubling the sampling bandwidth through time alternation is beneficial for many applications. For example, a radio transceiver architecture can increase the number of information signal carriers, thereby increasing the system data output. Doubling the sampling frequency can also improve the resolution of LIDAR measurement systems using the time-of-flight (TOF) principle. In fact, the uncertainty of the TOF measurement value can be reduced by shortening the effective sampling period.

Digital oscilloscopes also require a high sampling frequency Fs/input frequency FIN ratio to accurately acquire complex analog or digital signals. To acquire harmonic components of the input frequency, the sampling frequency must be a multiple of the input frequency (maximum value). For example, if the oscilloscope sampling frequency is not high enough and the higher-order harmonics are outside the Nyquist bandwidth of the analog-to-digital converter, a square wave will appear as a sine wave.

Figure 1 illustrates the benefit of doubling the sampling frequency of an oscilloscope front end. The 6GSPS sampled waveform is a more accurate representation of the sampled analog input. Many other test instrumentation systems, such as mass spectrometers and gamma-ray telescopes, rely on higher oversampling/FIN for pulse waveform measurements.

Figure 1: Time domain plot of a 247.77MHz signal sampled at 3GSPS and 6GSPS.

Increasing the sampling frequency has other advantages. Oversampling the signal also realizes the characteristic of improved gain in the digital domain through digital filtering. In effect, the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate for a fixed input bandwidth provides a 3dB improvement in dynamic range. Each doubling of the sampling frequency provides an additional 3dB of dynamic range.

Difficulties of time-alternation technology

The main difficulty in time interleaving is the accurate calibration of the sampling clock edges between channels and the compensation of the inherent variations between ICs. Accurately matching the gain, offset, and clock phase between the individual analog data converters is a big challenge, mainly because these parameters are frequency dependent. Unless these parameters can be accurately matched, dynamic performance and resolution will be degraded. Figure 2 shows the three main error sources.

Figure 2: Gain, offset, and timing errors produced by an alternating analog-to-digital converter.

Sampling Clock Phase Adjustment

Typically, a dual-channel interleaving converter system requires the timing of the analog-to-digital converter input sampling clock to be shifted by 1/2 clock cycle. However, the ADC083000 architecture uses on-chip interleaving with a clock frequency equal to half the sampling rate, or 1.5GHz for 3GSPS. Therefore, for a dual-channel system using two ADC083000s, the analog-to-digital converter input sampling clock edge must be shifted by 1/4 clock cycle or staggered by 90 (1.5GHz clock corresponds to 166.67ps).

The length of the clock signal trace that corresponds to a 1/4 clock period phase shift can be calculated relatively accurately. For FR4 printed circuit board material, the signal propagates at a speed of 20cm/ns (that is, 50ps is 1cm). For example, if the clock trace to one analog-to-digital converter is 3cm longer than the other, this will produce a phase shift of 150ps. The difficulty lies in accurately matching the additional 16.67ps time shift.

The ADC083000 has an integrated clock phase adjustment feature that allows the user to add delay to the input sampling clock to achieve a phase shift relative to the sampling clock of the other ADC. The ADC clock phase can be manually adjusted through the SPI bus using two internal registers. Phase shift can only be achieved in one direction, adding delay. The designer should determine the position of the two discrete ADCs, determine which one is "in front" and adjust its phase so that its sampling edge is 90o with the other ADC sampling edge, so that sub-picosecond adjustment resolution can be achieved.

Inter-channel gain and offset matching

In a dual converter interleaving system, the error voltages generated by channel gain mismatches can cause image spurs at Fs/2-FIN and Fs/4±FIN (assuming the input signal is within the first Nyquist band). An 8-bit converter has 28 or 256 codes. Assuming the full converter input range is Vp-p, the LSB size is 1V/256=3.9mV. We can conclude that the gain matching required for 1/2LSB accuracy is 0.2%.

The input full-scale voltage or gain of the ADC083000 can be adjusted linearly and monotonically using 9-bit data resolution. The adjustment range is ±20% of the nominal 700mVp-p differential value, or 560mVp-p to 840mVp-p.

840mV-560mV=280mV.

29 = 512 strides

280mV/512=546.88μV

[page]This fine-tuning allows for gain matching that is 0.2% greater than the above requirement.

Offset mismatch between adjacent channels will generate an error voltage, resulting in an offset spur at Fs/2. Since the offset spur is at the edge of the Nyquist band, designers of dual-channel systems can usually plan the system frequency accordingly and focus on gain and phase matching.

However, assuming that the required offset match is also 1/2LSB, the input offset of the ADC083000 can be linearly and monotonically adjusted from a nominal zero offset to a 45mV offset using 9 bits of resolution. Therefore, each code step provides a 0.176mV offset, with 9 bits of resolution achieving 1/2LSB accuracy.

Synchronization of digital outputs

Synchronizing the data streams from the two ADCs is critical to achieving the best combination of sampling speed and bandwidth. That is, if the outputs are not synchronized between the converters, no meaningful data can be acquired. Gigabit sampling rate ADCs can demultiplex the output data to reduce the digital output data rate. The user can choose to split the data rate by 1/2 or 1/4, depending on the processing power of the FPGA technology used.

The output acquisition clock (DCLK) is also separated and can be configured in SDR or DDR mode. However, demultiplexing introduces new considerations because there is now an added uncertainty in the coordination between the input sampling clock and the DCLK outputs of each ADC. To overcome this problem, the ADC083000 can accurately reset the relationship between the sampling clock input and the DCLK output, which is determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time as the sampling shared input clock, thereby achieving synchronization between multiple ADCs.

Digital Alternation Method

Analog calibration is a proven method to achieve high dynamic range, high overall integration solutions, and its integrated clock phase, gain, and offset adjustment functions provide high accuracy.

A viable alternative to analog calibration is a digital correction algorithm for alternating data. This approach seeks to correct data converter mismatches in the digital domain without any analog offset, gain, or phase correction. In theory, these algorithms can work independently without the need to implement calibration or understand the input signal. In addition, the convergence time of digital offset, gain, and phase correction factors is also a key system metric.

An algorithm developed by SP Devices is a proven digital post-processing method that meets these conditions. SP Devices' ADX technology continuously provides background estimates of the gain, offset, and time skew errors of the analog-to-digital converter without requiring any special calibration signals or post-processing. This algorithm is effective in correcting both static and dynamic mismatch errors.

The ADX technique estimates the error and reconstructs the signal with all the mismatch errors suppressed. The IP-core's error correction algorithm is effective for any input signal type. The result of this digital signal processing exceeds the time-alternating spectrum of the ADX core and eliminates the significant alternating distortion spurs associated with the mismatch.

A National Semiconductor reference board equipped with two ADC083000 3GSPS, 8-bit analog-to-digital converters demonstrates the SP Devices algorithm. The data converters are interleaved using ADX technology embedded in the board's FPGA. Figure 3 shows a block diagram of the 7GSPS digitizer card.

Figure 3: ADQ108 system block diagram with LMX2531 and LMH6554.

Figure 4 is a graph of the output spectrum performance of the SPDevicesADQ108 data acquisition card. It is worth noting that the spurious peaks are partially due to harmonic distortion, and the alternating spurious signals have been greatly reduced. For additional details on the data acquisition card, see: http://spdevices.com/index.php/adq108 .

Figure 4: Spectrum of combined analog-to-digital converter using ADX technology.