Low Noise Gain Selectable Amplifier

Data acquisition, sensor signal conditioning, and other applications with widely varying input signals require gain selectable amplifiers. Traditional gain selectable amplifiers use a switch in the feedback loop to connect a resistor to the inverting input, but the switch resistance degrades the amplifier's noise performance, adds capacitance at the inverting input, and increases nonlinear gain error. When using a low noise amplifier, the added noise and capacitance, nonlinear gain error, all affect accuracy in precision applications.

Figure 1. Using the ADA4896-2 and ADG633 to build a low-noise, gain-selectable amplifier to drive a low-impedance load.

The gain-selectable amplifier shown in Figure 1 uses an innovative switching technique that maintains the 1nV/&rad ic ;Hz noise performance of the ADA4896-2 while reducing nonlinear gain errors. This technique allows the user to select switches with minimal capacitance to maximize the bandwidth of the circuit.

Switching is implemented using the ADG633 triple SPDT CMOS switch in the following configuration: S1A and S2A are on at the same time, or S1B and S2B are on at the same time. Switch S1 is connected to the output of the feedback resistors, and switch S2 samples at either V1 or V2, where the switch resistors do not affect the gain. This reduces gain error while maintaining noise performance. With the values ​​shown, the first stage amplifier gain is 4V/V (“A” switch on) or 2V/V (“B” switch on). The number of switching gains can be expanded by adding switches, or by using multiplexers such as the 4:1 ADG659 or 8:1 ADG658.

Note that the output buffer’s input bias current flowing through the nonlinear on-resistance of the S2 sampling switch will create an offset. To compensate for this offset, an unused switch (S3B) is placed in the output buffer’s feedback path.

In addition, the bias current of the input amplifier causes a gain-dependent offset. Since the input amplifier and output buffer are on the same chip, the relative matching of their bias currents can be used to cancel out the offset variation. Placing a resistor equal to the difference between RF2 and RF1 in series with switch S2A reduces the offset-voltage difference.

The following derived formula shows that sampling at V1 produces the required signal gain with no gain error. RS represents the switch resistance. V2 can be derived in the same way.

(1)

(2)

Substituting equation 1 into equation 2, we get:

(3)

Note that if VO1 yields the desired signal gain with no gain error, then the buffered output VO2 will also have no gain error. Figure 2 shows the normalized frequency response of the circuit at VO2.

Figure 2. Frequency response of VO2/VIN.

About the Author

Nathan Carter [nathan.carter@analog.com] is a design engineer in the Linear and RF Group and has been in this position for over 10 years. He has degrees from California State Polytechnic University and Worcester Polytechnic Institute.

Chilann Chan [chilann.chan@analog.com] joined Analog Devices in August 2008 and is currently an applications engineer in the High Speed ​​Amplifier Group. Chilann received her B.E. from Dartmouth College and her M.S. in Electrical Engineering from Worcester Polytechnic Institute. While pursuing her degree, she researched how to use the “split ADC” architecture for a 16-bit, 1 MSPS differential successive approximation analog-to-digital converter.