Dynamic power management technology to meet the needs of multimedia processors

Active Power Management

On-chip power management techniques fall into two broad categories, managing active system power and managing standby power.

Active power management falls into three areas: Dynamic Voltage and Frequency Scaling Adaptive Voltage Adjustment and Dynamic Power Switching Static power management involves ensuring that idle systems are kept in a power-saving state until more processing power is needed, using so-called static leakage management techniques, which typically rely on several low-power modes from standby to power-off.

Let's look at active modes first. With DVFS , the clock speed and voltage can be reduced by software based on the performance needs of the application. For example, consider an application processor that integrates an advanced RISC microprocessor ( ARM ) with a digital signal processor (DSP). Although the ARM component can run at speeds up to 600 MHz, the system does not always need such high computing power. Typically, a predefined processor operating performance point ( OPP ) can be selected by software, where the voltage ensures that the processor operates at the minimum frequency that meets the system's processing performance requirements. To further increase the flexibility of optimizing power for different applications, an additional set of device core OPPs can be predefined for the interconnects and peripherals in the processor.

The software needs to send a control signal to the external regulator to set the minimum voltage according to the OPP. For example, DVFS applies to two supply voltages, VDD1 (the supply voltage of the DSP and ARM processors) and VDD2 (the supply voltage of the subsystem and peripheral interconnects), which provide most of the chip power (usually between 75% and 80%). When performing MP3 decoding, the DSP processor can be transferred to a low operating performance point, thereby significantly reducing power consumption for other tasks, and the ARM runs at a frequency of up to 125 MHz. In order to achieve the necessary functionality under the best power consumption, we can reduce VDD1 to 0.95 volts instead of using the maximum voltage of 1.35 volts to ensure an operating frequency of 600 MHz.

Adaptive Voltage Scaling (AVS), as the second active power management technology, is based on the differences generated during the chip manufacturing process and the device's operating life cycle. This technology is different from DVFS, where all processors use the same pre-programmed OPP. As you can imagine, for most mature manufacturing processes, the performance of the chips follows a certain distribution at a given frequency requirement. Some devices (the so-called "hot" devices) can achieve a given frequency at a lower voltage than other devices (the so-called "cold" devices), which is how AVS works - the processor senses its own performance level and adjusts the supply voltage accordingly. Dedicated on-chip AVS hardware implements a feedback loop that dynamically optimizes voltage levels to meet differences caused by process, temperature, and silicon die degradation without processor intervention.

Different requirements (Figure 1).

Software can set the AVS hardware for each OPP in operation, and the control algorithm sends instructions to the external regulator through the I2C

bus to gradually reduce the output of the appropriate regulator until the processor just exceeds the target frequency requirement. For example, developers can first design a voltage that meets all conditions, which is 0.95 volts at 125 MHz (above V1 in Figure 1). However, if a "hot" device using AVS technology is inserted into the system, an on-chip feedback mechanism will automatically reduce the voltage of the ARM to 0.85 volts or lower (above V2 in Figure 1). The

first two active power management techniques can keep a part of the device running at the ideal speed at the minimum operating voltage. In contrast, the third method - dynamic power switching (DPS) first determines when the device can complete the current computing task, and if it is not needed temporarily, it puts the device into a low-power standby state (Figure 2). For example, the processor will enter a low-power state while waiting for a DMA transfer to complete. The processor can return to normal operation within a few microseconds after waking up.