Phase-Shifted Resonant Full-Bridge Soft Switching Controller UCC3895-EEWORLD

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1. Introduction

UCC3895 is a phase-shifted resonant full-bridge soft-switching controller produced by Texas Instruments, USA. This series of controllers adopts advanced BCDMOS technology. The basic functions of UCC3895 are exactly the same as those of UC3875 series and UC3879 series controllers, and some new functions are added. The following introduces its features, pin functions, electrical parameters and working principles respectively.

2. Features and Pin Description

2.1 Features

(1) Output turn-on delay time is programmable and controllable;
(2) Adaptive delay time setting function;
(3) Bidirectional oscillator synchronization function;
(4) Voltage mode control or current mode control;
(5) Soft start/soft shutdown and controller chip select functions are programmable and controllable, single pin control;
(6) Duty cycle control range 0%~100%;
(7) Built-in 7MHz error amplifier;
(8) Maximum operating frequency reaches 1MHz;
(9) Low operating current, the operating current at 500KHz is only 5mA;
(10) The current in the undervoltage lockout state is only 150μA.

2.2 Pin Description

UCC3895 and UCC2895 phase-shifted resonant full-bridge soft-switching controllers are available in four package types: SOIC-20, PDIP-20, TSSOP-20 and PLCC-20. UCC1895 is available in two package types: CDIP-20 and CLCC-20. The following is an introduction to PDIP-20, and its pinout is shown in Figure 1. The pin functions of the UCC3895 series phase-shifted resonant controller are as follows:
·EAN (pin 1): inverting input of the error amplifier.
·EAOUT (pin 2): output of the error amplifier. Inside the controller, this terminal is connected to the non-inverting input of the PWM comparator and the no-load comparator, respectively, and is clamped to the soft-start voltage. When the voltage on this terminal is lower than 500mV, the output stage of the controller will be turned off by the no-load comparator. When the voltage on this terminal rises to 600mV, the output stage is turned back on.
·RAMP (pin 3): non-inverting input of the PWM comparator. In voltage mode or average current mode, this terminal is connected to the sawtooth signal on CT (pin 7); in peak current mode, this terminal is connected to the current signal. RAMP has a built-in discharge transistor, which is triggered during the oscillator dead time.
REF (pin 4): Precision 5V reference voltage output terminal. The reference power supply inside the controller not only supplies power to the circuit inside the controller, but also provides 5mA bias current to the external load. The reference power supply is only shut down in the undervoltage lockout state, and can continue to work in other failure states. In practice, this terminal should be connected to a low ESR and low ESL bypass capacitor, and its size should be at least 0.1μF.
GND (pin 5): Signal ground.
SYNC (pin 6): Oscillator synchronization signal output terminal. This terminal is bidirectional. When used as an output terminal, this terminal can output a clock signal. When used as an input terminal, this terminal can input an external synchronization signal to achieve synchronous operation of multiple controllers. This pin can also discharge the timing capacitor on the CT pin and the filter capacitor on the RAMP pin. The lower threshold of the synchronous circuit input voltage is 1.9V, and the upper threshold is 2.1V. In order to reduce the width of the synchronous pulse, a 3.9Ω resistor should be connected between the SYNC and GND pins.
CT (pin 7): oscillator timing capacitor access terminal. The charging current of the timing capacitor is controlled by the controller, and the peak voltage of the sawtooth wave on the timing capacitor is 2.35V. The oscillation period tOSC can be estimated by the following formula:

(1)
In the above formula, the unit of CT is farad, the unit of RT is ohm, and the unit of tOSC is second.
Note that the timing capacitor and the timing resistor
·RT (pin 8): the oscillator timing resistor access terminal. The charging current of the timing capacitor is a fixed value, and its size is determined by the timing resistor RT, as shown in the following formula:

(2)
DELAB (pin 9) / DELCD (pin 10): Output terminal AD delay control signal input terminal. The delay time should be added after one switch tube is turned off and before the other switch tube is turned on in the same bridge arm to create conditions for resonance. The delay time can be estimated by referring to the following formula:

(3)
In the above formula, the unit of VDEL is volt, the unit of RT is ohm, and the unit of tdelay is second.
DELAB and DELCD can provide a maximum sink current of 1mA. In practice, the stray capacitance of the DELAB and DELCD pins should be guaranteed to be less than 10pF.
·ADS (pin 11): delay time setting terminal. When the ADS pin is directly connected to the CS pin, the output delay dead time is zero. When the ADS pin is grounded, the output delay time is maximum. The delay time when the voltage on the CS pin is 2.0V is 4 times that when the CS voltage is 0V. The voltage on the output AD delay control signal input terminal is determined by the following formula:

(4)
In the above formula, the units of VCS and VADS are volts.
The voltage on the ADS pin must be limited to the range of 0V to 2.5V and cannot exceed the voltage on the CS pin. In addition, the minimum value of the voltage on the output AD delay control signal input should be clamped at 0.5V.
·OUTA/OUTB/OUTC/OUTD (pins 18, 17, 14, 13): drive output terminal. These four output terminals are composed of complementary MOS drive circuits, which can provide 100mA drive current and can drive FET drive circuits. OUTA and OUTB are fully complementary, and their duty cycle is close to 50%, which can drive half-bridge circuits. The same is true for OUTC and OUTD. For OUTA, the phase of OUTC has shifted; for OUTB, the phase of OUTD has also shifted.
·VDD (pin 15): bias power input terminal. This terminal needs to be connected to a low-ESR, low-ESL bypass capacitor, and its capacity must not be less than 1μF.
·PGND (pin 16): power ground. This terminal is the ground terminal of the high-current output stage.
SS/DISB (pin 19): Soft start/disable pin. This pin can be used to implement two independent functions: soft start and controller fast disable. The controller will be quickly shut down when one of the following four conditions occurs: (1) the voltage on this pin is lower than 0.5V; (2) or the voltage on REF drops below 4V; (3) the voltage on VDD drops below the undervoltage lockout lower threshold; (4) a zero-crossing fault occurs. When the fault is eliminated or the disable state ends, if the voltage on VDD exceeds the start threshold and the voltage on this pin drops below 0.5V during the soft shutdown process, the soft start mode will be entered. At this time, the current sinking on the SS/DISB pin will be equal to IRT. The soft start time is determined by the soft start capacitor on the SS/DISB pin. In addition, in order to limit the maximum voltage on this pin, a resistor needs to be connected in parallel with the soft start capacitor. Note that whether in soft start, soft shutdown, or disable state, the voltage on this pin will be actively clamped and its magnitude is equal to the voltage on the EAOUT pin.
· EAP (Pin 20): Non-inverting input of the error amplifier.

[page] 3. Rated parameters and main electrical parameters

The rated parameters of UCC3895 are shown in Table 1.

The main electrical parameters of UCC3895 are shown in Table 2.

Table 2 UCC3895 main electrical parameters
Note: (1) If not otherwise specified: VDD = 12V, RT = 82K, CT = 220pF, RDELAB = RDELCD = 10K, CREF = 0.1mF, CVDD = 0.1mF, TA = TJ.

4. Working Principle

UCC3895 is a phase-shifted full-bridge PWM controller made using BCDMOS technology, and its maximum operating frequency can reach 1MHz. This controller combines fixed-frequency PWM technology with zero-voltage switching technology to greatly improve the conversion efficiency of the converter at high frequencies. The basic functions of UCC3895 are the same as those of the UC3875 series and UC3879 series phase-shifted full-bridge PWM controllers, but improvements have been made in the control circuit, delay setting, and shutdown function. In addition, due to the use of BCDMOS technology, its bias current is significantly reduced compared to UC3875 and UC3879.
UCC3895 integrates a precision reference power supply, a high-frequency oscillator, a soft start circuit, an overcurrent protection circuit, a current detection circuit, a no-load comparator, an undervoltage lockout circuit, a drive output circuit, a reference voltage monitoring circuit, a delay setting circuit, a disabled state comparator, a PWM latch, a D flip-flop, etc. Its principle block diagram is shown in Figure 2.
Since the UCC3895 is basically the same as the UC3875 and UC3879 phase-shifted full-bridge PWM controllers in terms of function, the basic working principle of the UCC3896 will not be described here. The following only introduces the setting of the output delay time in the UCC3895.
The UCC3895 allows the user to set the delay time between the bridge arm drive pulses. In practice, the user can set the delay time according to equations (3) and (4). Figure 2-4-3 shows a schematic diagram of the external delay time programming resistor. The schematic diagram of the delay setting circuit is shown in Figure 2-4-4. The delay setting function is controlled by the ADS pin. When the ADS pin is connected to CS, GND, or a resistor divider between CS and GND, different delay time modulations can be achieved. If the ADS pin is grounded, it can be seen from equations (3) and (4) that VDEL will be proportional to VCS, and the delay time tdelay will decrease accordingly as the load increases. At this time, the maximum value of VDEL is 2V. If VADS is connected to the resistor divider between CS and GND, the delay modulation will be reduced due to the decrease in (VCS-VADS) term, which causes VDEL to drop. When the ADS pin is connected to CS, VDEL is limited to 0.5V and the delay time is zero. It can be seen that the delay modulation is the largest when the ADS pin is directly grounded. When the load gradually increases from light load to full load, VDEL will change between 0.5V and 2V. As the load continues to change, the delay time change ratio can reach a maximum of 4:1.

Reference address：Phase-Shifted Resonant Full-Bridge Soft Switching Controller UCC3895

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