A Design of Wideband Frequency Synthesis Based on DDS

Abstract: A broadband frequency synthesizer is designed for the high-performance DDS chip AD9858. The working principle of DDS is analyzed, the principle block diagram and implementation process of the broadband frequency synthesizer are given, and the software control process is explained in detail. The phase noise and spurious performance of the system are briefly analyzed and calculated in combination with the theory. Finally, the test results verify that the broadband frequency synthesizer based on AD9858 has good phase noise and spurious performance, achieving the expected goal.
Keywords: direct digital frequency synthesis; AD9858; YTO; phase detection At present,

there are three main methods for frequency synthesis: direct analog synthesis, phase-locked loop synthesis and direct digital synthesis. The direct analog synthesis method uses frequency multiplication (multiplication), frequency division (division), mixing (addition and subtraction) and filtering to generate multiple required frequencies from a single or several parameter frequencies. This method has a fast frequency conversion time (less than 100 ns), but there are too many spurious spectra and it is difficult to suppress. The phase-locked loop synthesis method completes the frequency addition, subtraction, multiplication and division operations through the phase-locked loop. This method has a simple structure and is easy to integrate. And the spectrum purity is high, and it is widely used at present, but there is a contradiction between high resolution and fast conversion speed, and it can generally only be used in large-step frequency synthesis technology. Direct digital synthesis (DDS) is a new frequency synthesis method that has developed rapidly in recent years. Its advantages are mainly that the output frequency is relatively wide, the frequency conversion time is short, the frequency resolution is extremely high, the phase change is continuous, the output waveform is flexible, and almost all components in DDS are digital circuits, which are easy to integrate, low power consumption, small size, light weight, high reliability, and easy to program control. It is very flexible to use, so it has a very high cost performance. DDS also has limitations, which are mainly manifested in: limited output frequency band range and large output spurious.

[page]1 DDS working principle
The basic principle of DDS is to use the sampling theorem to generate waveforms through the table lookup method. There are many types of DDS structures, and its basic circuit principle can be represented by Figure 1.

The phase accumulator is composed of an N-bit adder and an N-bit accumulator register in cascade. For each clock pulse fs, the adder adds the frequency control word k and the accumulated phase data output by the accumulator register, and sends the result of the addition to the data input of the accumulator register. The accumulator register feeds back the new phase data generated by the adder after the previous clock pulse to the input of the adder, so that the adder continues to add the frequency control word under the action of the next clock pulse. In this way, the phase accumulator continuously performs linear phase accumulation on the frequency control word under the action of the clock. It can be seen that the phase accumulator accumulates the frequency control word once for each clock pulse input, and the data output by the phase accumulator is the phase of the synthesized signal, and the overflow frequency of the phase accumulator is the signal frequency output by the DDS.
There are many DDS chips at present, but considering the suppression of spurious signals and the accuracy of frequency, the AD9858 chip is selected. The operating frequency of AD9858 can reach up to 1 GHz. Since the chip provides a divider at the clock input, its external clock can reach up to 2 GHz. AD9858 has an internal 10-bit digital-to-analog converter, and its frequency resolution (i.e., the number of bits of the frequency accumulator) is 32 bits, which can output signals up to 450 MHz. Its internally integrated programmable fast-lock charge pump (CP) and 150 MHz phase detector (PFD) make it very suitable for applications where high-speed DDS and phase-locked loops are combined; at the same time, it also provides an analog mixer, which can be used in applications where DDS, PLL and mixers are combined. In addition, the spurious suppression performance and harmonic suppression performance of AD9858 are also very outstanding.

2 Circuit Design
This solution mainly consists of an oscillator, a frequency division module, AD9858, a low-pass filter, a loop filter, and a YTO drive circuit. DDS is used to replace fractional frequency division to achieve frequency microstepping.
2.1 Hardware Principle
The working principle block diagram is shown in Figure 2.

The output of the YTO oscillator is used as the feedback signal of the phase-locked loop. Since the clock of AD9858 can reach up to 2 GHz, the feedback signal must pass through a four-frequency divider before it can be used as the reference clock fsysclk of AD9858. The reference clock fsysclk first passes through the built-in 2-frequency divider as the DDS adopted clock. The CPU calculates the frequency control word based on the YTO theoretical oscillation frequency, and then sends it to the AD9858 frequency control word register. The frequency f0 output by AD9858 passes through a 150 MHz low-pass filter and is phase-detected with the frequency reference fr. The phase detector here uses the phase detector integrated inside the AD9858. The phase detector outputs current information, which is provided by the internally integrated programmable fast lock charge pump (CP). This current cannot directly drive the YTO, so it is converted into an error voltage through a second-order passive loop filter, and then controls the YTO frequency modulation coil through the YTO drive circuit to lock the frequency of the YTO.
[page]2.2 AD9858 control and software flow
AD9858 has two working modes: point frequency mode and scanning mode. The frequency adjustment mode can be turned on as long as the control register (CFR) and frequency control word (FTW) are configured. The control register (CFR) is a 32-bit register controller with 4 bytes, corresponding to addresses 0x00, 0x01, 0x02 and 0x03. This solution uses the AD9858 built-in 150 MHz phase detector. The phase detector bit and polarity bit are configured during initialization, and the analog mixer is turned off.
The calculation formula of the frequency adjustment word:
frequency control word (FTW) = fox232/fsysclk (f0: output frequency fsysclk: reference clock)

3 Performance Analysis
3.1 Advantages of this Solution
DDS is a new frequency synthesis method that has developed rapidly in recent years. It has many advantages over previous frequency synthesis methods.
1) Small output resolution. The phase accumulator of AD9858 (reference clock frequency fc=600 MHz) is 32 bits with a resolution of 0.14Hz.
2) Short output frequency conversion time: The frequency conversion time of an analog phase-locked loop is mainly its feedback loop processing time and the response time of the voltage-controlled oscillator, which is usually greater than 1 ms. The frequency conversion time of AD9858 is mainly the digital processing delay of DDS, which is usually tens of ns.
3) Large frequency modulation range: The bandwidth of a negative feedback loop output reference frequency determines the stable frequency modulation range of the analog phase-locked loop; the entire DDS synthesizer is not affected by stability and is adjustable within the entire Nyquist frequency range.
4) Small phase noise: The biggest advantage of DDS over PLL is its phase noise. Since the phase of a digital sinusoidal signal is linearly related to time, the phase noise of the entire DDS output is smaller than the phase noise of its reference clock source. The phase noise of the analog phase-locked loop is double the phase noise of its reference clock.
5) Convenient design: The entire DDS includes a signal D/A converter, which is easy to implement during system design. Moreover, the current DDS no longer requires a dedicated RF design, and simple digital control reduces the complexity of the hardware.
3.2 Analysis of the spurious performance of this solution
The main sources of spurious signals are the spurious output of the DDS and the leakage of the PLL phase-locked frequency fr. Since the spurious output of DDS is rich, when the spurious distribution is within the loop bandwidth, the spurious suppression ratio in the band is deteriorated due to the frequency multiplication effect of PLL:
S=20lg(N)dB Where: N is the division ratio of PLL;
when the spurious bit of DDS is outside the PLL loop bandwidth, it is suppressed by the loop, thereby improving the spurious suppression ratio:
S=20lg(N)dB
In theory, the output spurious of DDS is determined by the following formula:
SQR=1.76+6.02B+20Log(FFS)+10Log(Fsos／Fs)(dB)
Where: B is the number of bits of the output DAC
FFS is the percentage of the DAC full scale
Fsos is the oversampling rate
Fs is the Nyquist rate
For example: for AD9858DDS, the output full scale is 0.7 of 150 MHz, and the clock is 900 MHz, its spurious is
SQR=1.76+6.02x104-20log(0.7)+10log(900／300)=63.63(dB)

[page]4 Test results
The key and difficulty of this system is to examine the spurious index of AD9858 output. The test conditions are AD9858 reference clock 600 MHz and DAC output 150 MHz. The experimental results are shown in Figure 4 below. The near-end spurious is better than -80 dBc and consistent with the data of AD9858, meeting the design requirements.

5 Conclusion
With the development of digital electronic technology, direct digital frequency synthesis has been increasingly widely used. DDS is favored as a frequency synthesis technology, but it also has some problems. With the development of digital technology, I believe that DDS will have a better performance.