An automatic zero adjustment circuit with a voltage range of plus or minus 10V and 12-bit resolution and its working principle analysis

Function of the circuit

When the signal from the sensor is superimposed with the DC component, if the amplification factor is increased, the amplifier saturation will cause the amplification factor to decrease. In many cases, the signal obtained is often smaller than the DC component. At this time, it is very convenient to use an automatic zero adjustment circuit like the one listed in this section. It can perform zero adjustment within the voltage range of negative and positive 10V with a resolution of 12 bits.

How the Circuit Works

OP amplifier A1 is a differential amplifier circuit. The voltage output generated by the DA converter is the same as the DC offset in the input signal. After subtraction, the output is zero. A2 is an amplifier with a magnification of 10 times. Because the minimum resolvable voltage output by A1 is 4.88MV, if this signal is immediately input into the zero-crossing comparator, it is easy to cause instability, so the comparator adds a 50MA hysteresis voltage. Perform an equivalent comparison of 5MV.

Comparator output: using an up-down counter, and determining the direction of automatic zeroing by selecting up or down counting.

Inputting a clock pulse greater than 4096KHZ will start automatic zeroing and stop at an appropriate time. Assuming that the time for the voltage to change from -10V to +10V is T, the pulse frequency is 4096/T. If T=1 second, when a 4096KHZ clock is input for 1 second, the output voltage will definitely become zero. There is no stability requirement for the clock signal, and a clock oscillator composed of NE555 can be used.

The 12-bit counter is loaded with 800H when the power is turned on. At this time, the DA converter is set to zero volt output, there is no DC offset, and it is in standby mode. The selected DA converter is different, and the selected data is input in advance at the data preset end of the counter.

The power supply of the counter and NAND gate IC is connected to the VDD marked with ★. In order to prevent the count from being cleared due to a momentary power outage, the best way is to use a battery as a backup.

Component Selection

After zero adjustment with this circuit, when high gain amplification is required, attention should be paid to the selection of IC. A low-drift OP amplifier should be selected. If the input signal contains noise, the zero adjustment accuracy will decrease. A low-pass filter can be added to the input end, or C1 marked with a ★ can be added. The FC value is FC=1/2πC1*100*10 to the power of 3.

Resistors R1~R4 should be selected with small temperature coefficients, otherwise the zero point will deviate due to the influence of the surrounding temperature.

Adjustment

Input clock pulses from jumper JP1 or JP2, and verify that the DAC output is a sawtooth wave of plus or minus 10V. (If the wiring between the counter and DAC is wrong, it will not be a straight waveform, but a jagged waveform.) Then open or short the input. Input zero clock. If normal, the DAC output should be zero, and the A1 output should also be zero. If the counting direction is reversed, it will oscillate at a low frequency, and the counting direction must be reversed.