Solve system problems with multiphase digital power solutions

Challenges

Current processor, graphics and storage systems use multiphase power solutions. These multiphase solutions provide the response and regulation performance of a very high switching frequency converter while switching individually at a more moderate frequency. They can also provide higher output currents than are practical for single-channel buck converters. The advantage of multiphase power comes from phase interleaving. By interleaving the phases at uniform intervals (for example, 120° intervals in a three-phase interleaved converter), the output ripple inherent to each phase is reduced to an average level by the other phases, thereby reducing the overall output ripple. This allows the use of lower PWM switching frequencies to achieve a given output ripple design target while improving efficiency by reducing switching losses.

Managing a multiphase power system presents its own unique problems, including phase shedding for light load efficiency and system redundancy, and phase current balancing for system lifetime. Implementing these functions in a traditional analog power supply can be difficult, but using a digital controller can easily accomplish these tasks. In this case study, a digital power solution is introduced that has the advantages of a multiphase synchronous buck converter while using a digital method to close the voltage control loop and manage the phases under different load and thermal conditions for optimal power performance.

Solution

Such a system consists of up to six interleaved synchronous buck converters controlled by a single microprocessor, as shown in Figure 1.

Figure 1 Digitally controlled multi-phase interleaved synchronous buck

TI's 32-bit TMS320F2806 digital signal controller (DSC) runs at 100 MHz and is targeted for power supply applications. In this case, voltage mode control is implemented in software using a single-channel 2-pole 2-zero digital compensator sampled at the PWM switching frequency. The resulting duty cycle value is then passed to each buck phase (except for any duty cycle adjustments for phase balance). System output voltage feedback is obtained using an on-chip 12-bit analog-to-digital converter (ADC). MOSFET temperature is available across the ADC for monitoring purposes, and an on-chip inter-integrated circuit (I2C) port provides support for PMBus™ communication. A UCD7230 gate driver is specifically designed for synchronous buck applications, providing dual-channel 4-A MOSFET drivers with TI's TrueDrive™ output architecture, cycle-by-cycle current limiting, and a built-in low-offset, high-gain, differential current sensing amplifier.

Phase cutting and phase adding

Phase shedding provides a method to improve power supply efficiency and reliability. Dynamically reducing the number of operating phases under light load conditions generally results in improved efficiency. When load demand increases, a shedding phase can be reactivated. Similarly, shedding a failed phase or a phase operating outside of a marginal state helps maintain system performance by rebalancing the interleaving between the remaining phases. In applications that require extreme reliability, a spare phase can be brought online to replace the failed phase, i.e., an N+1 redundant design. Regardless of the reason for shedding a phase, the interleaving angle of the remaining phases (or added phases in an N+1 redundant design) should be readjusted to maintain optimal performance. For example, shedding a phase from a three-phase 120° interleaved converter should separate the two phases by 180°.

The PWM elements of the TMS320F2806 controller support software synchronization and phase control. Each PWM output has a phase synchronization register that offsets its count value from the count value of the first PWM output. This allows the phase angles of all interleaved buck phases to be not only statically configured during system initialization, but also dynamically readjusted during system operation.

Figure 2a shows an oscilloscope screen capture of a three-phase interleaved buck converter with 120° interleaving (conditions: 10V input, 2V output, 3A load, and 300 kHz PWM switching). Scope channels 1 to 3 show the individual phase voltages, while channel 4 shows the interleaved output voltage (all scope channels are AC coupled). With all three phases running, the output ripple is 4.9 mV (0.25% of the output voltage). Without adjusting the angles of the two remaining phases (see Figure 2b), cutting out phase 2 causes the output ripple to increase by 86%, or 9.1 mV. After software adjustment of the two remaining phases to achieve 180° interleaving (see Figure 2c), the ripple is reduced to 7.9 mV. While still larger than the initial value (because a two-phase system cannot achieve as low ripple as a three-phase system), it is a 13% improvement over the unadjusted remaining phase angles.

Figure 2a Three-phase interleaved synchronous buck output

Figure 2b: When the interleaving is 120°, phase 2 is removed and phases 1 and 3 are retained.

Figure 2c Phase 1 and Phase 3 are adjusted to achieve 180° interleaving

Phase current balance

To optimize power component reliability and longevity, it is desirable to have each phase in a multiphase system share the power load equally. Due to component differences between power switches and inductors, as well as asymmetries in board layout and heat sinking, the currents flowing through the phases are different. Basic balancing methods involve measuring the phase currents and individually adjusting the PWM duty cycle required for each phase to balance the currents. The current imbalance dynamics are very slow, so the sampling rate of the balancing loop can be low, on the order of a few tenths of a second or even a few seconds. Therefore, the additional computational burden on the microprocessor is negligible. To reduce the effects of sensor noise, the balancing loop rate current readings are oversampled and the current measurements for each phase are averaged over time. Simple low-gain full behavior "only" control algorithms are often used to close the balancing loop. Balancing can be performed on each phase during each loop iteration using the average phase current as a reference. Alternatively, phase current balancing can sometimes be achieved by balancing the highest and lowest current phases measured at that moment with each other. Regardless of which method is used, all phase currents will eventually converge to the same value.

PWM accuracy is a common problem encountered when performing phase current balancing. Consider a 10V input as a 2V output synchronous buck converter driven by a 300 kHz PWM with a 100 MHz PWM clock. The PWM accuracy on the buck output will be 30 mV, or the equivalent of 1.5% of the 2V output. Typically, this granularity will be one or even two orders of magnitude greater than the fine duty cycle regulation required to achieve phase balance and avoid limit cycling in the balancing control loop. The F2806 controller provides a solution to this problem and uniquely enhances the high accuracy of the PWM module. This high accuracy PWM provides edge positioning of ~150 ps. This equates to 0.45 mV output accuracy for the buck example above, or 0.02% of the 2V output. This solution provides high accuracy and good phase current balancing.

in conclusion

This article describes a digitally controlled multiphase interleaved DC/DC buck system that implements voltage mode regulation control with phase shedding and phase gain and multiphase current balancing. Implementing these features using a traditional analog controller would be very challenging, but using a microprocessor-based digital controller can easily accomplish these tasks. The perfect combination of the F2806 digital signal controller and the UCD7230 gate drive and current sensing amplifier provides a complete signal control solution with stand-alone on-chip flash memory, synchronized high-precision PWM modules, ADCs for measuring feedback signals, and PMBus communication capabilities.