Circuit design for bootstrap operation under light load

In Figure 1, the green box shows the added circuitry that solves the voltage drop problem of the bus voltage signal. The waveform in Figure 2 shows how this problem occurs in the buck converter IC1B, where the output voltage VBUS drops below the regulation point at a fixed rate when there is no load. The other traces in Figure 2 show that the VBUS drop occurs when the bootstrap voltage drops below its 8.66V threshold (Trace 3), causing the buck converter to stop switching. This situation is more serious when the bus voltage is close to the input voltage.

During freewheeling operation in DCM (discontinuous conduction mode), the output signal (Figure 3, trace 4) tends to settle to the bus voltage after the inductor L1 is discharged. This action prevents the charging of the bootstrap capacitor CBS, which eventually causes the bootstrap voltage in Figure 2 to drop below 8.66V. As a result, the buck converter stops operating.

The circuit in the green box in Figure 1 solves this problem. It starts by tapping the input signal to the bootstrapped high-side driver, generating an inverted and delayed short pulse that controls Q2. Once Q2 is activated, it forces the output signal low immediately, giving CBS a chance to charge. R8, R9, R10, R11, and C9 set the on-time of Q2. This period must not exceed the dead time of the PWM (pulse width modulation) signal. If Q2 is on for too long, the efficiency of the converter will decrease, or CBS may not be fully charged. Insufficient charging of Q2 affects multiple component values ​​and operating parameters, such as Q2's on-time, and you may have to adjust the delay time empirically to accommodate these effects. The values ​​in Figure 1 provide a 1 μs on-time for Q2 and a 450 ns delay time at a switching frequency of 70 kHz.

The Q5 network is optional. Its purpose is to disable the operation of Q2 when the P_ON/off signal is not needed to connect to the open collector Q6. The lower half of IC1A drives Q2. The value of R6 must be chosen by experimentation. If the resistor value is too low, a large current pulse will be generated when Q2 is activated. On the other hand, too high a resistor value will not charge CBS enough.

Resistor R7 and capacitor C8 control the delay time between the falling edge of the bootstrap high-side driver input signal and the rising edge of IC1A's LVG (low voltage) pulse. Figure 4 shows the waveforms of the same converter after adding the circuit. At this point, VBUS (Trace 1) remains stable, while the output signal of the buck regulator switches continuously without the switching gaps shown in the waveform in Figure 2.