Design and implementation of a low-power general-purpose voice processing platform

Abstract: This paper introduces the scheme of low-power general voice processing platform based on TMS3.0VC5510A, and implements a variety of voice compression algorithms and algorithm-based adaptive power consumption control on it, which meets the requirements of low power consumption.

Voice signal processing has been widely used in the field of communication, and the digitization of voice transmission is an important link in the fully digital mobile communication system. The combination of high-quality, low-rate voice coding technology and high-efficiency digital modulation technology provides modern mobile communications with system capacity, communication quality and spectrum utilization that are superior to analog mobile communications. The development of modern mobile communications also puts forward higher requirements on the power consumption of the system, so low-power, high-performance DSP has been increasingly widely used in various fields. This paper introduces the use of TMS320VC5510 A, the latest developed by Texas Instruments (TI), in the United States , using its data processing capabilities and low power consumption characteristics, and combining MSP430F149 to increase the control capability of the system, to realize various voice algorithms in real time, which has important reference value for the actual development of voice processing systems, and the platform has been applied to actual products. 1 Composition and principle of speech processing system 1.1 Composition of speech processing system There are many kinds of speech algorithms, which require the front end of the speech processing system to provide digital sampling signals that meet the algorithm accuracy requirements. Therefore, the front end A/D and D/A are required to have high sampling rate and sampling accuracy. The speech processing system also has real-time requirements. In some applications, speech encoding and decoding algorithms, encryption and decryption algorithms, channel encoding and decoding algorithms, and even modulation and demodulation algorithms are required to be implemented in the same chip. Therefore, the system is required to have strong data processing capabilities and large storage space. In the usual DSP application system, DSP plus memory, A/D, D/A and peripheral interface can be realized. However, more and more occasions require the system to complete communication and control with external systems, such as human-machine interface, channel transmission equipment and other control functions. These can all adopt the MCU + DSP structure to make up for the poor control capability of a single DSP system. After careful selection and comparison, the final hardware structure design of the speech processing system is shown in Figure 1. Speech processing system block diagram Figure 1 Speech processing system block diagram 1.2 Speech processing system principle As shown in Figure 1, the analog voice passes through the bandpass filter formed by the power amplifier and is converted into a 8,000Hz digital signal through the analog/digital converter (ADC) of the TLV320AIC10. The accuracy of the sampling signal is 16 bits, and the amplitude requirement for the input analog signal is -3.3 to 3.3V. The digitized voice signal is transmitted to the internal buffer of the DSP (TMS320VC5510A) through the synchronous serial port (McBSP), sent to the encoder for encoding, and the obtained data stream is transmitted to the terminal through the synchronous serial port (McBSP) and the channel interface, and transmitted after channel encoding. The code stream received from the channel is decoded by the terminal and transmitted to the internal buffer of the DSP through the synchronous serial port (McBSP), and sent to the decoder for decoding. The obtained digitized voice is then transmitted to the analog/digital converter (ADC) of the TLV320AIC10 through the synchronous serial port (McBSP) and converted into an analog signal output. In order to enhance the control capability of the hardware platform, the DSP (TMS320VC5510A) communicates with the MCU (MSP430F149) through the host interface (HPI). And the memory Flash (SST39VF800A) is added to ensure offline operation. 2 System Specific Implementation 2.1 Main Chip Selection and Introduction The TLV320AIC10 used in this platform is a general-purpose low-power 16-bit A/D, D/A audio interface chip launched by Texas Instruments , which is suitable for voice and broadband audio processing; its digital interface adopts synchronous serial port mode, which can be easily connected to the synchronous serial port (McBSP) of DSP, where SCLK provides bit clock signal, FS provides frame synchronization signal, DIN is serial data input, and DOUT is serial data output. The serial port connection method of TLV320AIC10 and DSP is shown in Figure 2. The TLV320AIC10 works in the master mode, and the DSP's synchronous serial port (McBSP) works in the slave mode. The clock of the synchronous serial port is provided by the SCLK of the TLV320AIC10, which is 2.048MHz. Schematic diagram of the connection between TLV320AIC10 and TMS320VC5510A Figure 2 Schematic diagram of the connection between TLV320AIC10 and TMS320VC5510A

Compared with TMS320VC54X, the main digital signal processing chip of the system, TMS320VC5510 A, has lower power consumption, higher code execution efficiency, and is fully compatible with the instructions of TMS320VC54X. It has the following characteristics. (1) Rich resources. 32-bit wide external memory interface (EMIF), 2 20-bit wide timers, 6-channel DMA controller and 3 multi-channel buffered serial ports (McBSP), 16-bit enhanced host parallel interface (EHPI), 8 general purpose pins (GPIO). (2) Strong data processing capability and fast operation speed. TMS320VC5510A adopts an improved Harvard structure. The DSP of C55X performs 3 data reads and 2 data writes simultaneously in one bus cycle. It adopts a parallel dual MAC structure, which provides more powerful parallel processing capabilities. (3) Low power consumption. TMS320VC5510A adopts high-performance static CMOS technology, with an I/O supply voltage of 3.3V and a core supply voltage of 1.6V. It also has multiple low-power working modes, which effectively reduces system power consumption. The core static power consumption is 0.112mA/MIPS, and the I/O static power consumption is 0.148mA/MIPS. The core dynamic power consumption is about 0.628mA/MIPS. In order to increase the control function and expansion capability of the platform, TI's microcontroller MSP430F149 is used . This chip is an ultra-low power Flash microcontroller of TI, with a 16-bit RISC CPU as the core. Its memory module has the lowest energy consumption among all internally integrated Flash memory products in the industry. It has an ultra-low power working mode, namely the active mode (MSP430 only) and: 400?ZiA/MHz, 3.0V. MSP430F149 can provide 5 working modes, with the lowest power consumption reaching 1?ZiA/MHz; using the IAR development environment, it can be directly programmed in C language, which is convenient and fast to develop. 2.2 Interface circuit design between CODEC and DSP Since CODEC (TLV320AIC10) and DSP (TMS320VC5510A) are both high-speed chips provided by TI, the two can be fully matched in speed and timing, and can achieve seamless connection between chips (see Figure 2 for the connection diagram of the two). The working clock of TLV320AIC10 is provided by MSP430F149 through internal frequency division to provide 2.048MHz clock to MCLK of TLV320AIC10 as system clock. TLV320AIC10 works in master mode and provides serial clock SCLK and frame synchronization signal FS to TMS320VC5510A. The frame synchronization signal FS is output through the FS pin after the internal 256 frequency division of TLV320AIC10, which is an 8 000Hz positive pulse signal with a pulse width of one SCLK clock. The reset signal of TLV320AIC10 is provided by the general I/O pin of DSP. The PWRDWN pin is used to control the working state of TLV320AIC10: when this pin is set low, TLV320AIC10 stops working and is in IDLE state, thus saving power; when this pin is set high, TLV320AIC10 is in normal working mode. In this example, a pull-up resistor is added to this pin to ensure that TLV320AIC10 is in normal working state. DSP uses McBSP0 to connect with TLV320AIC10, and the McBSP0 general serial port works in slave mode. BCLKR0/BCLKX0 are the shift clocks for receiving and sending the general serial port, BFSR0/BFSX0 are the frame synchronization signals for receiving and sending, BDR0 is the receiving data pin, and BDX0 is the sending data pin. The received data can be triggered by the frame synchronization signal to trigger an interrupt and be read and written by the interrupt service program; it can also be directly converted to a specific buffer through the DMA channel. The frames of TLV320AIC10 can be divided into master frames and slave frames. The sampled data is transmitted in the master frame, and the internal registers of TLV320AIC10 are configured in the slave frame. When TLV320AIC10 works in 15+1 bit mode, the last bit of the master frame determines whether the next frame after the master frame is a slave frame or still a master frame. During the initialization process of TLV320AIC10, it is initialized in this way to configure the 4 registers inside TLV320AIC10. The process of DSP configuring TLV320AIC10 registers is shown in Figure 3. TLV320AIC10 initialization flow chart Figure 3 TLV320AIC10 initialization flow chart After the DSP main program configures the internal registers of TLV320AIC10, it will set the corresponding interrupt handler, open the corresponding interrupt mask, and transmit the voice sample points through the interrupt service program. 2.3 Interface circuit and communication method between MCU and DSP DSP (TMS320VC5510A) provides an enhanced host interface (EHPI), which can work in two modes: data address multiplexing and non-multiplexing. In this example, the data address multiplexing mode is adopted. The specific connection method between MCU (MSP430F149) and DSP EHPI is shown in Figure 4, and the interface timing of EHPI is shown in Figure 5. MSP430F149 and TMS320VCAA10A EBPI connection diagram Figure 4 MSP430F149 and TMS320VCAA10A EBPI connection diagram EHIP interface timing diagram Figure 5 EHIP interface timing diagram The key control signal line functions of the host interface are briefly described as follows. HD[15:0]: HPI data line, bidirectional, three-state bus. In multiplexing mode, addresses and data are transmitted through this 16-bit bus. HA[19:0]: HPI address bus. In multiplexing mode, HA[1] is used as the HCNTL1 signal line, and HA[2] is used as the HAS signal line. HCS: The chip select signal line of HPI. As the chip select signal when the MCU accesses the DSP, it is always kept low during the access process. In this example, in order to save the I/O port line of the host, it is always kept low.

HR/W: HPI read/write signal line. It marks the communication direction between MCU and DSP. If the signal line is high, it means that MCU reads data from the storage space of DSP; if it is low, it means that MCU writes data into the storage space of DSP.

HDS1/2: HPI data control signal. It can adapt to the data control signal of different types of MCU. To set HCNTL2 high, the connection method in this example is to control HCNTL1 through P2.1 of MSP430F149 . HRDY: HPI ready signal. DSP uses this signal to inform MCU whether the current host interface is accessible. If it is low, the host interface of DSP is busy and MCU cannot access it; if it is high, it can be accessed. HCNTL0/1: HPI access control signal. In multiplexing mode, these two signals determine whether the MCU accesses the internal register of the HPI interface of DSP. HAS: HPI address control signal. In multiplexing mode, it is directly set high. HMODE: HPI mode selection signal. If it is set high, HPI works in non-multiplexing mode; if it is set low, HPI works in multiplexing mode. HINT: Host interrupt signal. When the DSP sets this signal line low, it means that the DSP requests a host interrupt. Therefore, a pull-up resistor should be added to this signal line. HBE0/1: HPI byte enable signal. TMS320VC5510 A sets this signal low and ignores this signal. MSP430F149 controls the corresponding communication mode by writing corresponding data to the three registers inside the DSP host interface. In multiplexing mode, these three registers are HPIC (control register), HPIA (address register), and HPID (data register). In order to improve the access speed in multiplexing mode, the DSP's HPI interface also provides another data register. When the MCU accesses continuous addresses, it can select to use this data register to continuously access the DSP internal memory through HCNTL0/1, and the corresponding address register will automatically increase after each access to this data register. The communication between the MCU and the DSP is completed through interrupts. Among them, the MSP430F149 triggers the DSP interrupt by accessing the HPIC register and setting the DSPINT position 1 in it, while the DSP triggers the MCU interrupt by setting the HINT signal line low. In the current hardware platform, the MCU implements the read and write operations of the DSP host interface by setting the I/O port line. You can choose to start the DSP through the host [4]. The block diagram of the startup process is shown in Figure 6. HPI startup method flow chart Figure 6 HPI startup method flow chart 3 System software optimization to reduce power consumption As mentioned above, low-power devices are used in the design of the hardware platform, which belongs to the static technology in low-power design. In the specific implementation of the system software, dynamic adjustments can be made according to the execution of the algorithm to achieve the purpose of reducing system power consumption. Since the DSP uses an internal programmable phase-locked loop (PLL) to generate the clock, the processor can dynamically change the operating speed according to the immediate demand for computing power. Although the system provides several low-power modes, the corresponding wake-up times are different. In practice, power consumption and wake-up time should be considered comprehensively according to the specific situation. Since the MCU has a strong event response capability and the DSP has a strong data processing capability, the system operating frequency and DSP working state can be dynamically changed according to different algorithms through the MCU, thereby reducing system power consumption. For example, when running the 600, 1,200, and 2,400 bps speech algorithms independently developed by Tsinghua University on this platform, it is necessary to dynamically configure the different data operation requirements of different algorithms. The DSP uses the 8.192 MHz clock provided by the MCU and multiplies it through the integrated DPLL to obtain the required main clock. Since part of the system code is in 54-compatible mode, in the main function of the system software, when no encoding or decoding operations are required, the system can be in a normal state, that is, IDLE1 or IDLE2 state. More specific management can be managed using the IDLE domain mechanism of the c55x series [6]. The three states are described as follows: NO IDLE: The timer, universal serial port, and kernel are all in normal working mode. IDLE 1: The timer and universal serial port are in normal working mode, the kernel is in IDLE state, and is awakened by an interrupt. IDLE 2: The timer, universal serial port, and kernel are all in IDLE state, and are awakened by an interrupt. For different algorithms, due to the different data operation requirements, the minimum system frequency that can ensure the operation of the algorithm is also different. By dynamically adjusting the system's working state according to different data operation requirements, the purpose of reducing power consumption can be achieved to the maximum extent, thereby realizing power consumption control for different computing amounts. In actual use, when the DSP: runs the 600SELP algorithm, the system works at 32.768MHz; when running the 1200SELP algorithm, the system works at 40.960MHz; when running the 2400SELP algorithm, the system works at 24.576MHz. Compared with the single operation at 81.92MHz, the system power consumption is reduced by 41%, 36%, and 48% respectively, which greatly reduces the system power consumption. The hardware platform has successfully run algorithms such as G.723.1, G.729A/B and CVSD, and has achieved good results, with broad application prospects.