A method for generating 5Hz three-speed three-phase SPWM waveform

Abstract: This paper introduces the hardware circuit and software design of 5Hz/50V, 60V, 70V three-phase SPWM waveform generation, and gives

Output waveform of the inverter.

Keywords: inverter software design

A 5Hz variable frequency power supply for textile machines has three output voltages of 50V, 60V and 70V due to different working conditions. This article will focus on the hardware circuit and software design method of using the single-chip microcomputer 8098 as the main control chip to generate these three levels of SPWM waveforms.

The principle of SPWM computer implementation is still based on the intersection of the sine control wave and the triangular carrier to determine the on-off time of the switch device. With different sampling methods, the software programming method is also different, and it must also be combined with the working mode of the hardware timer, so there are many different implementation methods. This paper adopts the method of using high-level language to calculate the corresponding pulse width data offline according to the principle of regular sampling method, and the output is realized by the 8098 single-chip microcomputer table lookup, realizing the inverter output of three-phase line voltage of 50V, 60V, 70V three-speed 5Hz low-frequency sine voltage.

1 Principle of regular sampling method

Since the intersection of the sine wave and the triangular wave is arbitrary, the pulse center is not equidistant within a cycle, so the pulse width expression is a transcendental equation and cannot be expressed by a simple analytical expression. In order to simplify the calculation workload and facilitate engineering implementation, the pulse center can be changed from unequal to equidistant. Sampling is performed at a fixed point of the triangular carrier to determine the time when the PWM wave appears and ends, regardless of whether the sine wave and the triangular wave intersect at this moment. Engineering practice has proved that the error caused by this is completely negligible. In this way, the arbitrariness of the intersection of the two waveforms is intentionally eliminated, and the algorithm is changed from an unsolvable transcendental equation to a simple solvable trigonometric equation. 〖1〗

This article adopts the PWM waveform formation principle based on regular sampling technology and sample-and-hold principle, which is common in engineering. Its sampling frequency is equal to the carrier frequency, and the sampling is performed at the positive peak of the carrier triangle wave. The pulse is always symmetrical to the trough of the carrier triangle wave, as shown in Figure 1. According to Figure 2, we can obtain the pulse width t2 corresponding to each moment of the triangle wave.

Since the sampling time and sampling value are clearly defined, the pulse width and the leading and trailing edge positions can be calculated. If the carrier triangle wave amplitude UTM is set to 1, the control sine wave amplitude UC is M, the triangle inclination is α, the slope is 4/T2 (T2 is the triangle wave period), and the sampling value is MsinωCt. The proportional formula can be obtained from the similar geometric relationship between the right triangles OBB' and OCC':

(t2/2)/(T2/2)=(1+MsinωCt)/2

Thus, the pulse width time t2=T2(1＋MsinωCt)/2 is obtained

The interval time can be obtained from the symmetry of the pulse waveform:

t1=t3=(T2－t2)/2=T2(1－MsinωCt)/4

According to the expressions of t1, t2, and t3, the appearance and end time of each pulse in one cycle of the sine wave can be completely determined. From the graph in Figure 1, the regular sampling method actually uses a series of step-shaped step waveforms to approximate the sine wave. Therefore, the higher the carrier frequency ωC, that is, the more sampling points, the higher the accuracy.

For a three-phase inverter, since the three phases are symmetrical and have a phase angle difference of 120°, we have [2]:

t2a=T2(1＋MsinωCt)/2

t2b=T2[1+Msin(ωCt-120°)]/2

t2c=T2[1+Msin(ωCt+120°)]/2

And: t2a＋t2b＋t2c=3T2/2

t1a＋t1b＋t1c=t3a＋t3b+t3c=3T2/4

2 Sampling 8098 to implement SPWM wave

Figure 1 Regular sampling PWM waveform

Figure 2 Regular sampling method of PWM wave

2.1 Hardware Circuit

Select 8098 single-chip microcomputer HSO0, HSO1, HSO2 to output three SPWM waves, and get six SPWM signals after passing through the phase-splitting delay shaping interlocking circuit in Figure 3. In this way, the hardware circuit is used for phase splitting and the hardware circuit is used for delay to generate dead time, so that the power switch on the same bridge arm of the inverter completes the dead time control logic of first shutting off and then turning on, and avoids the direct-through accident caused by software errors, so that the SPWM signal of the drive circuit itself has excellent reliability.

Figure 3 Split phase delay shaping interlocking circuit

The size of the dead time is mainly determined by the following aspects: when the drive circuit works in the on and off modes, there is a difference in the signal transmission delay time; the drive of the upper and lower power switching devices of the inverter bridge arm cannot be completely consistent; the power device is not an ideal switch, and its on and off delays are not equal.

Therefore, we need to comprehensively consider these factors to determine the length of the dead time and give a certain margin. In short, we need to fully estimate the minimum delay time tonmin from the control signal to the power tube when it is turned on and the maximum delay time toffmax from the control signal to the power tube when it is turned off. Then the dead time can be set to toffmax-tonmin. In practice, the dead time is slightly larger than toffmax.

This paper uses IGBT as the power switch tube of the inverter and EXB841 as the driving module. The maximum delay time of EXB841 is 1.5μs, and IGBT generally does not exceed 3μs, so the dead time in this paper is set to 5μs.

The circuit principle of Figure 3 and the determination of parameters are analyzed below. It can be considered that there is no signal delay on the comparator. Since this circuit uses LM339, its output is OC output and the input impedance is very large. Figure 4 shows the waveforms of each point in the circuit of Figure 3. The potential of the potentiometer RP tap is the comparison voltage UR of the four comparators. Considering that the output current of HSO is small, A1 is used as a buffer and B1 is used as an inverter. The voltages UA1 and UB1 are charged and discharged by the RC circuit to complete the delay, and then compared with the reference voltage UR by A2 and B2 to obtain the outputs OUTA and OUTB. The addition of waveforms OUTA and OUTB can obtain a negative pulse representing the dead time, and its width is the dead zone TD.

Figure 4 Waveforms at each point

In FIG3 , the RC parameters of group A and group B circuits are the same, and group A is taken as an example to illustrate the determination of the RC parameters. When HSO changes from low level to high level, the initial value of the voltage UA2 on CA is zero, and since LM339 is an OC output, a charging circuit of 5V power supply, RA1, RA2, CA and ground is formed, with a time constant of tA1=(RA1+RA2)CA. When UA2 rises to UR, comparator A2 flips; when HSO changes from high to low, CA discharges through RA2 and injects current into the output of comparator A1, with a time constant τA2=RA2·CA. Since RA2RA1 (here RA2 is just to limit the instantaneous inhaled current from CA when it discharges), tA1tA2. Since UA2=UR=VCC, τA1=（RA1+RA2）CA≈RA1CA. Solving this equation, the dead time TD is as follows: In this article, the dead time is 5μs, VCC=5V, when UR=2.5V, RA1CA=7.2μs

Therefore, CA is set to 360P, RA1 is 20kΩ, and RA2 is 100Ω. In order to ensure the consistency of the three-phase dead time, the capacitor is a high-end precision monolithic capacitor, and the resistor RA1 is a resistor bank. The resistor bank adopts an integrated manufacturing process and has a relatively high precision. R is the comparator output pull-up resistor, which can be a 10kΩ resistor bank.

2.2SPWM software design

Since the output of this system is fixed at 5Hz and the voltage is divided into three levels of three-phase AC, there is no frequency conversion problem, and the table lookup method is more suitable.

This avoids the more complicated single-chip online calculation. Its main advantage is that the use of table lookup can increase the carrier frequency, thereby reducing the harmonic component, and give the CPU free time to perform other management. The data table can be obtained by high-level language calculation.

(1) Obtaining the data table

According to the principle of regular sampling method, as long as the period and the number of pulses in one period and the modulation ratio m of the corresponding output amplitude are given, any pulse in one period of the output waveform can be obtained.

The output cycle of this system:

T = 1/5 Hz = 0.2 s = 0.2 × 106 μs

Modulation ratio: UOUT is the inverter three-phase output line voltage, and Ed is the DC voltage on the DC side. This system requires UOUT to have three levels of 50V, 60V, and 70V, and Ed = 270V, so there are three corresponding m values. Therefore, three sets of data tables corresponding to the three voltage levels need to be generated.

Since the inverter output is a three-phase sine wave with the same amplitude, but the phase is 120° different from each other, they have the same pulse wave in each cycle, that is, the pulse width and number are exactly the same, so only one phase data table is required. When looking up the three-phase table, the lookup is performed in a way that the phase is 120° different from each other. In order to facilitate the implementation of 8098, a set of data in this table is: [t2/2, t1]. For P pulses in one cycle (0~2π), the 8098 in this article uses a 6MHz crystal oscillator with a clock period of 0.5μs, and the time resolution of HSO is 8 times the clock period, that is, 4μs. Therefore, (t2/2)N, (t1/2)N also need to be quantized according to 4μs, and the maximum quantization error is 2μs. In addition, the data loaded into HSO should be 16-bit word length data, so the data in the data table are stored in 16-bit word length. The data storage format of the Nth pulse is: [(t2/2)N/0.000004]16bTTS, [(t1/2)N/0.000004]16bTTS. A data table consists of 201 groups of such data. Corresponding to the three gears of 50V, 60V, and 70V, we get three groups of data tables, which are stored in three areas with TABLE50, TABLE60, and TABLE70 as the table headers. At run time, as long as the address pointer is located in one of the three table headers, the corresponding output voltage can be achieved.

In practice, high-level language offline programming is used to obtain three sets of data tables and store them in EPROM. When the PWM wave output is required during program operation, it is only necessary to look up the table to obtain the value and set the timing.

(2) Waveform output

The SPWM wave output is completed by 4 HSOs. HSO0, HSO1, and HSO2 are used as three-way SPWM wave output ports. HSO3 is a timer interrupt as the time base. The HSO3 timer interrupt time is T2/2. Each interruption outputs half a pulse wave. To output 201 pulse waves in one cycle, 201×2=402 interruptions are required. In the interrupt service program, the CPU loads the t1, t2, T/2 values ​​and the control word to each HSO port, and then returns to the main program. Repeating the above process can output continuous SPWM waves. The SPWM wave output block diagram is shown in Figure 5.

Figure 5 SPWM wave output block diagram

3 Conclusion

The current and voltage waveforms of the SPWM wave generated by the above method and outputted by the inverter with a frequency of 5 Hz are shown in Figure 6. It can be seen from the figure that the waveform is correct and good.

(a) Voltage waveform (b) Current waveform
Figure 65Hz current and voltage waveform