Implementation process of a low-power system chip

Abstract: With the advancement of semiconductor process technology, the integration of system chips is getting higher and higher, and power consumption has become one of the key factors to consider, especially for portable devices. This article describes a multi-power, multi-voltage low-power system chip implementation process. This process is based on the IEEE1801 (UPF) standard and uses EDA tools from Synopsys and MentorGraphics to easily implement the entire RTL-GDSII process.
Keywords: low power consumption; design for testability; multi-power and multi-voltage; power shutdown

0 Introduction
With the advancement of CMOS semiconductor technology, integrated circuits have entered the era of system on chip (SoC) design, which has greatly improved the integration and clock frequency, resulting in a sharp increase in chip power consumption. Power consumption has become another important factor in integrated circuit design in addition to area and timing, so low-power design has become the focus of academic and industrial circles. The introduction of low-power technology has brought new challenges to chip design and implementation. These challenges include the division of voltage domains, data exchange and management between EDA tools, etc. Based on the IEEEl801 standard Uni-fied Power Format (UPF), this paper uses EDA tools from Synopsys and Mentor Graphics to implement a complete low-power flow design "from RTL to GDSII" including testability design. Part 1 of this paper describes low-power technology and terminology. Part 2 describes the system chip designed in this paper. Part 3 describes the entire design process and the EDA tools used. Part 4 is a summary.

1 Low power technology
The power consumption of digital CMOS circuits mainly comes from three sources, namely switching power consumption Pswitching, short-circuit power consumption Pshort-circuit and leakage power consumption Pleakage, which are divided into two categories: dynamic power consumption (Pswitching+Pshort-circuit) and static power consumption (Pleakage), as shown in formula (1).

Among them, α is the switching activity factor, CL is the effective capacitance, VDD is the operating voltage, fclk is the clock frequency, ISC is the average short-circuit current, and Ileak is the average leakage current. At present, various methods for reducing power consumption have been proposed. The mainstream technologies include clock-gating and multi-threshold voltage. Advanced technologies include multi-voltage (MV) power shutdown (MTCMOS Pwr Gating), multi-voltage and power shutdown with state retention (MV&Pwr Gating with State Retention), low-voltage standby (Low-VDD Standby), dynamic or adaptive voltage and frequency scaling (Dynamic or Adaptive Voltage&Frequency Scaling, DVS, DVFS, AVS, AVFS), well bias (Well Biasing, VTCMOS), etc. In order to implement these technologies, it is necessary to divide the voltage domain (Power Domain, PD) during design, form different working modes (Power Mode, PM) and add special devices, such as power shutdown devices (Power Switches), level conversion devices (Level Shifter, LS), isolation devices (Isolation Cell) and state retention devices (State Ret-ention Cell), etc. In the chip design of this article, clock-gating, multi-voltage and power shutdown technologies are used.

2 Summary of this design
The chip design of this paper is shown in Figure 1. It has 40,000 registers and 200,000 logic gates, divided into seven voltage domains, PD TOP (top), PD1, PD2, PD3, PD4, PD5 and PD6, of which PD6 works at 1.2V and the rest work at 1.8V. There are three voltage modes in normal working mode, namely PM1 (PD1 is off, the rest are on), PM2 (PD TOP and PD1 are on, the rest are off) and PM3 (PD TOP is on, the rest are off). The enable signals (ps en and iso en) of the power shutdown device and the isolation device are generated by the power mode controller (PMC) in the normally open area PD TOP.

3 Low-power design process
As shown in Figure 1, an isolation device must be inserted into the output of each shutdown voltage domain to prevent the instability of the output after the power supply of the voltage domain is turned off from affecting the normal operation of other voltage domains. Since the operating voltage of PD6 is 1.2V and the others are 1.8V, level conversion devices must be inserted into the input and output of PD6. These low-power design intentions are written into the UPF file, and the EDA tool implements the designer's ideas based on the UPF. The entire design implementation process includes RTL code synthesis, testability design, layout and routing, physical verification, and equivalent formal verification of the netlist, as shown in Figure 2.

3.1 The
synthesis of RTL code uses Design Compiler (DC), and the input files are UPF, library file with power information (pg.db), RTL code and timing constraint file (SDC. During the synthesis optimization process, the tool will automatically insert level conversion devices and isolation devices at the corresponding positions according to UPF. After the optimization is completed, the correctness can be checked with the check_mv_desing command. The netlist output by DC and the RTL code are verified by Formality.
3.2 Testability Design
Perform testability design in the integrated netlist that has passed the equivalent formal verification. First, use MBISTArchitect to perform the intrinsic self-test (MBIST) of static random access memory (SRAM). The input files include the netlist and the model of SRAM, and the output is a netlist with self-test circuit. Secondly, use BSDArchitect to complete the boundary scan test. The input files include the netlist and
the model of the input/output interface circuit, and the output is a netlist containing the boundary scan circuit. Finally, use DFTCompiler to complete the logic scan test. The input files are UPF, timing constraint file and netlist, and insert The dft command completes the connection of the scan chain. Since UPF is not used when doing intrinsic self-test and boundary scan test circuits, the check mv desing command should be used to check after the scan chain is inserted.
If the level conversion device and isolation device are missing, insert them with insert_mv_cell. If they are redundant, delete them with remove_mv_cell command. DFT Compiler outputs the netlist, new UPF', SPF, DEF and timing constraint files. After completing the netlist of testability design and the integrated netlist, perform equivalent formal verification.
3.3 Layout and routing
Using IC Compiler performs layout and routing. The input files include UPF', timing constraint file, and netlist. The output files are netlist and timing constraint file. The output netlist must complete equivalent formal verification. After completing layout and routing, the netlist uses MVRIC to check low-power design, Star-RCXT to extract parasitic parameters, PrimeTime to sign off on timing and power consumption, and finally
MVSIM and VCS to complete post-simulation. Finally, Calibre is used to complete physical verification and output GDSII file. The final chip layout is shown in Figure 3.
3.4 Automatic test vector generation
The netlist after layout and routing and the SPF file output by DFT Compiler are sent to TetraMAX for automatic test vector generation. The design in this paper generates 2576 vectors with a fault coverage rate of 98%, and VCS is used to complete the post-simulation of the test vector.

4 Conclusion
This paper describes a low-power system chip implementation process. Using this process, a system chip containing 40,000 registers and 200,000 equivalent logic gates was implemented and tape-out verified, and the results achieved the expected goals.