Power supply planning for an electronic system authentication chip

Abstract: In order to protect the developed electronic products, an electronic system authentication chip based on hard encryption technology is designed by using ASIC method. In the back-end physical design, in order to optimize the area of ​​the final chip and meet the requirements of power consumption and timing, the pre-design method is used to estimate the power consumption and analyze the wiring congestion of the chip. According to the analysis results, the chip utilization rate is improved, and a detailed power planning is carried out for the IR Drop violation in the pre-design, including the connection of the global power network, the design of the power ring and the power bar, which finally meets the power consumption requirements, achieves timing convergence and area optimization.
Keywords: system authentication; power planning; power analysis; voltage drop

0 Introduction
In order to prevent the developed electronic products from being illegally cloned, an effective method is to use hard encryption technology to protect the electronic products. Hard encryption technology refers to relying on specific hardware to achieve system protection. The host needs to access the corresponding hardware for authentication before it can work normally. It has the advantages of high anti-decryption strength, good stability and compatibility.
The electronic system authentication chip studied in this paper is implemented by using the method of application-specific integrated circuit (ASIC) design based on hard encryption technology. Due to the special algorithm on ASIC, PCB and some hardware may be copied, but the encrypted data of ASIC cannot be copied, and the confidentiality is stronger. The chip uses the RSA encryption algorithm, which is a representative of the asymmetric key cryptographic system. Its security lies in the fact that it is relatively easy to find two large prime numbers p and q; but there is currently no effective way to decompose p and q from the product N of p and q. Some experts suggest that ordinary companies can use a 1,024-bit key to ensure the security of data, so the system authentication chip uses the RSA encryption algorithm with a key of 1,024 bits.
The electronic system authentication chip uses SMIC 0.18μm 6-layer metal process and is physically designed on the SoC Eneounter platform. In order to understand the wiring congestion level and power consumption of the entire chip, the chip is pre-designed before the formal design; the wiring congestion of the chip is analyzed through the results of the pre-design, and the power consumption after layout and routing is estimated. On the basis of analyzing the pre-design, a detailed power supply plan is carried out for the chip based on the problems existing in the pre-design, and a reasonable power supply network is designed for the entire chip, so that the final design achieves area optimization and meets the requirements of power consumption and timing.

1 Power consumption estimation
The pre-design adopted a utilization rate of 75%, and a rough layout planning was carried out for the electronic system certification chip, and only a power loop with a width of 10 μm was designed. In order to make the analysis results of the chip power consumption closer to reality, the chip was laid out, clock tree synthesis and detailed wiring were carried out. Under the premise of timing convergence, power consumption analysis was carried out. The working voltage VDD was 1.8 V, and the total power consumption of the chip was 115.41 mW, including switching power consumption (Switehing Power), internal power consumption (Internal Power) and leakage power consumption (Leakage Power). However, there is an IRDrop violation in the chip (that is, the voltage drop in the chip exceeds 5% VDD). As shown in Figure 1, the dialog box in the upper left corner lists the places where IR Drop violations exist, and the specific location is in the dark area in the layout. In general, a 5% voltage drop will increase the line delay by 10% to 15%, which will cause timing violations and put the chip in an abnormal working state. Therefore, detailed power planning is required in subsequent designs.

After detailed routing with 75% utilization, it was found that the routing congestion in the layout was not serious, and the routing resources of Meta15 and Meta16 were relatively ample. Some studies have shown that the chip cost is proportional to the fourth power of the chip area. In order to reduce costs, the chip area should be reduced as much as possible. After repeated attempts, it was determined that the chip utilization was 80%, the chip core area was about 2.474 mm2, and the total area was about 3.5 mm2, which was about 0.12 mm2 less than the preset timing.

2 Power planning
In the pre-design stage of the electronic system certification chip, there was an IRDrop violation, so the power supply network of the chip must be designed through power planning to eliminate the IR Drop violation. The overall steps of power planning include the connection of the global power network, power/ground pad planning, power ring design, and power bar design.

2.1 Connecting the global power supply
The connection of the global power supply network refers to connecting the corresponding ports and networks to the appropriate power supply and ground network, so that the design of the entire chip power supply network and subsequent steps can be completed smoothly. You can connect by selecting the "Connect Global Net" option in the "Floorplan" menu list, or you can connect by entering the command "global-NetConnect-nect" in the terminal.
2.2 Power/ground pad planning
2.2.1 Determine the number of power supply pads
According to the power consumption value of the chip core in normal operation obtained from the power consumption analysis, the minimum number of power/ground pads required to power the core can be calculated according to formula (1).

In the formula: PAVG is the average power consumption of the chip core in normal operation; VPAD and IPAD are the power supply voltage and the maximum current that can be provided by the I/O pad that powers the core under normal conditions. Here, VPAD is the operating voltage VDD of the chip core; k is the adjustment factor. According to the actual situation of the chip, the minimum value is 1~2 and the maximum value can be 5~10.
In the SMIC 0.18μm I/O unit description document, the minimum metal width in the power/ground unit structure is given. The minimum metal width of the PLVDD* and PLVSS* series is 70 μm. Based on the given minimum metal width, the current that the corresponding I/O Pad can provide can be calculated, as shown

in formula (2): Where: Cd is the upper limit of the current density determined by the process. Generally, Metall to Meta15 are 1.0 mA/μm. In the case of copper process, the top metal Meta16 is 1.6 mA/μm at 110℃. Therefore, the I/O unit used in the design can provide 70 mA of current.
The result of pre-running the back-end design at 75% utilization shows that the chip power consumption is 115.41mW and the operating voltage is 1.8V. Substituting it into formula (1), it can be obtained that the number of core power supply pads required for the electronic system certification chip is 1 pair, and the number of pads that power the I/O unit is also 1 pair, and the ground pads of the two are short-circuited to make the power ring of the entire I/O unit have better ESD protection performance.
2.2.2 Determination of the power supply pad position
The power supply pad can play a good role in isolating interference and reducing noise in the chip. The following factors can be considered in the placement of the power supply pad:
(1) Place the power/ground pad in the signal pad that jumps at the same time to isolate it and prevent the signals from interfering with each other;
(2) It is best to use ground pads to isolate the two ends of the clock signal pad to shield the interference of signal jumps on the clock signal;
(3) In order to ensure uniform power supply of the entire chip core power network and reduce voltage drop and electromigration, the power/ground pad is evenly distributed around the chip;
(4) Since the reset signal pad is easily affected by noise, the power/ground pad can be used to reduce noise;
(5) The arrangement of the pad also needs to consider the final chip packaging. Its arrangement should be convenient for the lead during packaging, try to avoid the crossover of welding lines during packaging, and comply with the design rules of the packaging (such as the minimum pad spacing, the largest corner and the maximum gold wire length, etc.).
2.3 Design of the power ring
In the power planning stage, the power ring refers to the Core Ring, which is the power ring that supplies power to the chip core. It is a bridge connecting the power supply I/O pad and the standard unit. Through the Core Ring, the power supply I/O pad can be used to supply power to the standard unit and the hard core.
The total width of the power ring is determined by the power supply peak current of the entire chip and the current density allowed in the manufacturer's design rules. The total width of the required power ring Wring can be estimated by formula (3):

Where: Ip is the peak current of the chip; Cd is the upper limit of the current density given by the manufacturer's process library, which is the same as the definition in formula (2); k is the adjustment factor, which is determined according to the distribution of the power supply I/O units of the chip.
Since the Core Ring has four sides, each side bears 1/4 of the current, so the total width of the power ring divided by 4 is the total width of each side of the Core Ring. In the design of the power ring, the width of a single power ring cannot exceed the wide line rule specified by the manufacturer to avoid drilling. The calculation of the width of a single power ring w is as follows:

Where: n is the logarithm of the power ring.
From formula (3), it can be obtained that the total width of the required power ring is 64.117μm. In order to effectively reduce the chip area occupied by the power ring, the design adopts a double-layer power ring design, using Meta13 and Meta15 horizontally; Meta14 and Meta16 vertically, so n is 2, and w is 8.015 μm from formula (4). In order to reserve a certain amount of redundancy for the power consumption of the entire chip, and the width of the metal line is wide enough to reduce the circuit failure caused by electromigration, it is concluded from repeated practice that the width of a single power ring is 15 μm, which can meet the requirements of electromigration and voltage drop of the chip. The designed power ring is shown in Figure 2.

Finally, according to the maximum current value required for the Rom core to work provided in the document, design the Block Ring to power the Rom.

2.4 Design of Power Strip
In order to solve the problem of IR Drop violation in chip preset timing, the voltage drop inside the chip is reduced by designing a power strip. The power strip is divided into horizontal and vertical. The width of the vertical power strip is set to WV, the width of the horizontal power strip is set to WH, the spacing of the vertical power strip is set to SV, and the spacing of the horizontal power strip is set to SH. Generally speaking, since there are many power/ground lines of standard cells in the horizontal direction, the required horizontal power strip lines are much less than the vertical power strip lines.
For the setting of WV, WH and SV, SH, there are several empirical rules:
(1) WV is generally taken as an integer multiple of the vertical wiring pitch (Pitch), the purpose of which is to make full use of the wiring channel. The value cannot be too large, and generally does not exceed 4 times the width of the minimum two-input NAND gate.
The pitch of each metal layer has a corresponding definition in the physical library. The pitch of Meta11 to Meta16 defined in SMIC's 0.18μm process library is shown in Table 1.

The width of the minimum two-input NAND gate in SMIC's 0.18μm process library is 1.98μm. Therefore, if Meta12 or Meta14 is used as the vertical power strip, WV takes an integer multiple of 0.66 between 0.66 and 7.92μm; if Meta16 is used as the vertical power strip, WV takes an integer multiple of 0.95 between 0.95 and 7.92μm.
(2) The value of WH is generally an integer multiple of the height of the standard cell, usually 1 or 2 times; the width of the power strip line can also be set to an integer. The height of the standard cell in the SMIC 0.18μm process library is 5.04μm, so the width of the horizontal power strip is 5.04μm or 10.08μm.
(3) In the selection of the metal layer of the power strip, according to the provisions of LEF, select even layers in the vertical direction and odd layers in the horizontal direction. Since high-level metal has a smaller parasitic resistance, using high-level metal routing can effectively reduce voltage drop.
(4) After determining the width of the power supply line, it is necessary to calculate its spacing SV and SH. This can be calculated according to the method proposed in the literature. For
the power grid shown in Figure 3, based on the estimated width of the horizontal/vertical power supply metal strips inside the Core, the total current JTOTAL with power consumption P can be calculated as P/VDD.

Assuming that there is a 5% voltage drop at point A in Figure 3, the effective resistance at point A is:


Where: RVW and RHW are the reference square resistances in the vertical and horizontal directions, respectively.
Assuming that N is the logarithm of the vertical power strip and M is the logarithm of the horizontal power strip, their values ​​are:

Finally, if the designed vertical power strip and horizontal power strip are evenly distributed in the chip core, the spacing SV of the vertical power grid and the spacing SH of the horizontal power grid are:

First, the vertical power strip is designed. Since the power strip is located inside the chip, it will occupy a certain amount of wiring resources, and the wiring device generally gives priority to the bottom metal to start wiring, so the wiring resources of the top metal are relatively abundant. In addition, the top metal is thicker than other metal layers and has better electrical performance. Using more top metal is very helpful in reducing IR Drop. Therefore, Meta16 is selected as the vertical power strip. According to the actual situation, the width WV of the vertical power strip is taken as 7.6 μm. The width W of the chip core area is 1578.085μm, and the height H is 1567.44μm. Therefore, the above formula shows that the total number of power strips N required for the system certification chip is 5.749. Take N=6, that is, 6 pairs of Meta16 power strips with a width of 7.6μm are evenly placed in the chip core area, and the spacing between each pair of power strips is 225.44μm.

Next, the horizontal power strip is designed. The high-level metal Meta15 is selected as the horizontal power strip, and the width is 5.04μm. According to the above formula, the total width of the required horizontal power strip is 87.424μm. However, in fact, so many power strips are not needed, because the power/ground of the standard cell is connected to the two ends of the chip core through Metal1 and connected to the vertical power strip. The design has 312 rows of standard cells, each with a pair of 0.4μm horizontal power strips, which is equivalent to 312×0.4=124.8μm power strips, which is larger than the total width of the required horizontal power strips and is sufficient to supply the entire chip, so that the voltage drop in the horizontal direction is less than VDD×5%=0.09 V.
In order to make the voltage drop in the horizontal direction smaller, 3 pairs of Metal5-layer horizontal power strips with a width of 5.04μm are designed, evenly distributed in the chip core area. The design results of the power strip are shown in Figure 4.

After the subsequent physical design, under the premise of meeting the timing convergence, the results of the VDD power consumption analysis of the power network after the final detailed wiring are shown in Table 2. It can be seen that the design of the power planning has greatly improved the IR Drop inside the chip. Finally, there is no IR Drop violation inside the chip, and the power consumption requirements are met, as shown in Figure 5.

3 Conclusion
This paper mainly discusses the power planning of electronic system authentication chips based on the RSA algorithm. Based on the SMIC 0.18μm process, the chip is first pre-designed. By analyzing the power consumption estimation and routing congestion of the pre-design, the chip utilization rate is improved and the chip area is reduced during the formal design; and through detailed power planning (including the design of double-layer power rings and power strips, etc.), the voltage drop violation in the preset timing is eliminated, so that the electronic system authentication chip finally meets the power consumption requirements and timing convergence.