High-precision hot-swap and power monitoring

These circuits are often used in systems that need to remain fully functional throughout their operating life, such as servers, network switches, redundant array of independent disks (RAID) storage, and other forms of communications infrastructure, which are called high-availability systems. If a component fails, it needs to be removed from the system and replaced with a fully functional component, all while the power remains on and the system continues to operate, a process called "hot swapping."

To perform the above operations safely, a hot-swap controller is needed to control the inrush current and prevent the backplane power supply that powers other systems from losing power. During normal operation, the controller can also prevent short circuits and other overcurrent faults. The latest series of hot-swap controllers from Analog Devices also integrates high-precision digital power monitors to support high-precision system power measurement (see Figure 1).

Figure 1. Many high-power systems require hot-swap devices to safely control inrush current during power-up and provide fault protection.

As the power requirements of these systems increase, efficiency becomes more important, and previous designs with loose tolerance and severe insertion power loss are no longer feasible. The ADM1275 not only provides high-precision power monitoring to report system power, but also has many features specifically designed to reduce the typical losses associated with hot swapping, such as insertion loss of the sense resistor and MOSFET.

Below we will discuss the design process of a typical high-current blade server hot-swap design, including component selection considerations.

System Specifications
This example assumes the following conditions:
● ADM1275 controller
● VIN=12V (nominal)
● VMAX=12.6V
● ITRIP=70A
● CLOAD=5000mF
● TMAX=65℃
● RPOWERUP=10Ω (static load resistance during system power-up)
For simplicity, many device tolerances are not considered in the calculation. These tolerances should be considered when designing for worst-case conditions.

Sense Resistor Selection
The selection of the sense resistor is primarily based on the desired circuit breaker operating current. However, the ADM1275 also includes an adjustable current limit threshold that allows the current limit to be fine-tuned above the limit provided by the limited standard sense resistor values. The sense voltage can be programmed in the range of 5 to 25 mV. Such a low sense voltage and programming flexibility allows the power loss of the sense resistor to be reduced and the size to be reduced.

The breaker timer (current fault spike filter) start point is typically 0.8mV below the regulation point, which means that to set a trip point of 70A (19.2mV), the regulation point needs to be set to about 73A (20mV).

This is not a common value, consider the closest value of 0.25mΩ, which is obtained by connecting two 0.5mΩ resistors in parallel. According to the above equation, the required detection voltage is reversed: VSENSE = RSENSE × ITRIP = 0.25 mΩ × 73 ≈ 18.25mV. The ISET pin can use a voltage divider to obtain the required voltage from the VCAP reference voltage (see Figure 2).

Figure 2

VISET = VSENSE × 50 = 18.3mV × 50 = 0.915V
Using a 2.7V VCAP reference voltage, assuming R1 = 100kΩ, the bottom resistor is 51.1kΩ. The given ISET voltage can provide a circuit breaker trip point of approximately 70A and a regulation current set point of 73A. Assuming the worst-case DC current can be as high as 75A (including allowable errors), the maximum DC current of each resistor is approximately 42A, including a margin of approximately 10% to cope with current imbalance. Therefore, the power can be calculated as: PRSENSE = ITRIP2 × RSENSE = (42A)2 × 0.0005Ω = 0.882W. Each sense resistor should be able to dissipate more than 1 W of power (including temperature reduction factors), and 2W or 3W resistors are recommended to reduce operating temperatures. A series of 10Ω resistors should be used to average all these nodes and send the results to the controller.

Summary of key component selection in this section:
RISET(TOP)=100kΩ
RISET(BOT)=51.1kΩ
RSENSEx=0.5mΩ×2(2/3W)
RAVGx=10Ω×4

MOSFET Selection
The first consideration in selecting the appropriate MOSFET is the on-resistance RDSON specification, which is designed to ensure that the power losses in the MOSFET are minimized when the MOSFET is fully enhanced in normal operation.

The ADM1275 provides a high voltage gate drive that ensures a minimum VGS of 10 V, thus maintaining the lowest rated RDSON. The gate drive circuit achieves this while still ensuring that the maximum VGS requirement of 20 V is not violated under fault conditions.

As the temperature of a MOSFET increases, its power rating is reduced, a process called “derating.” The RDSON specification determines the maximum junction temperature of the MOSFET and, therefore, the derating that can be applied to the SOA parameter. Additionally, operating the MOSFET at high temperatures may reduce its reliability.

We start by estimating the required RDSON. As mentioned previously, the worst-case maximum DC current is 75A, and then using the maximum ambient temperature specified in the first section, we can estimate the power losses in the MOSFET.

First, make a few assumptions:
● RthJA = 40C/W (maximum)
● TjMAX = 120℃
(this is the highest preferred junction temperature, far from any chip limit)
Calculate the junction temperature rise, then calculate the power of a single FET, then calculate the total RDSON, which is too small for a single FET, so try 3 FETs in parallel, subtract 10% to provide some margin for imbalance caused by layout asymmetry, and consider a factor of 1.4 to allow for some derating.
Use this as the target RDSON to find suitable candidates. The search can be narrowed down to FETs with the following characteristics:
● VDS = 25/30V (20V is a possible option, but not preferred)
● VGS = 20V
● RDSON ≤ 1.4mΩ
After selecting the appropriate MOSFET, the RDSON derating should be determined using the MOSFET data sheet's RDSON vs. TJ graph.

Using a TjMAX of 120°C, Figure 3 shows that at 120°C, RDSON increases by about 1.52 times to about 1.824mΩ (assuming 1.2mΩ at 25°C). In general, it is best to keep the junction temperature below 120°C to improve reliability. Assuming the maximum RDSON of the MOSFET is 1.83mΩ, the power per FET is 1.39W.

Figure 3

This is determined by the thermal resistance of the MOSFET at ambient temperature and is given in the data sheet. Size, airflow, adjacent heat sources and added copper also affect this value and care must be taken to ensure that the rated conditions are met. For this design, the expected power dissipation in the MOSFET is approximately 1.39W and the worst case temperature rise is an increase of 55.6°C above the ambient temperature. Therefore, the junction temperature of the FET can be determined by the following equation: TJ=TA+T
This temperature is lower than the selected maximum value of 120°C, so the risk of thermal runaway should be avoided. When using multiple MOSFETs in parallel, a 10Ω resistor should be connected in series with the gate of each MOSFET to prevent parasitic oscillations.
Summary of key specifications/component selection in this section:
QX=selected 1.2mΩ MOSFET
RthJA=40k/W
RGATE=10Ω(x3)

Power Derating Factor
Having determined the maximum junction temperature, we can now determine the maximum derating factor. This factor will be used to derate all SOA parameters to confirm that the solution is stable and reliable over the entire temperature range.
The derating factor can be calculated using the following formula:

Summary of key indicators/component selection in this section:
DF=2.5

The
ADM1275 utilizes a foldback technique to protect the MOSFET from overcurrent faults or short circuits. The output voltage is monitored via a voltage divider on the FLB pin, and the current limit is adjusted based on the VDS of the MOSFET. Figure 4 shows an example of this relationship.

Figure 4

When the output voltage is 0, a lower clamp prevents the current limit from approaching 0. The clamp voltage is fixed at 0.2V (FLB pin, or 4mV Vsense), which is equivalent to about 16A for this design. As the output voltage increases, the current limit slowly increases. The threshold is set by a voltage divider on the FLB pin, using a reference voltage equal to VSENSEREG X 50. This voltage should be low enough so that any expected VOUT load step does not affect the current limit. The PWRGD output is also derived from the level at the FLB pin. If the target value is 10.3V, it can be seen that the top resistor of the voltage divider is 100KΩ and the bottom resistor is 12KΩ.
Summary of key specifications/component selection in this section:
VPG=10.3V
RFLB_TOP=100kΩ
RFLB_BOT=12kΩ

MOSFET Safe Operating Area Analysis
The next step is to examine the SOA curve in the MOSFET data sheet to determine how long it can withstand the worst-case FET power and determine the appropriate timer capacitor value. In a multi-FET solution, it must be assumed that a single FET can dissipate 100% of the power during this type of power-up event, because the Vth levels of the FETs may be different and only one FET may be turned on during regulation.

In the short circuit condition, we can assume that the Vds of the FET is about 12.6V (assuming the source is connected to GND). The actual value may be lower than this due to the trace impedance.

However, the relationship between FET power and Vout is not monotonic. As shown in Figure 5, the worst-case power of the FET is about 6.3V (50% of Vin).

Figure 5

De-rating it by a derating factor of 2.5 gives 135 A. On the SOA graph for the MOSFET, the 6.3V line intersects the 135A line at approximately 0.8 ms (see Figure 6).

Figure 6

It should be noted that the SOA power line for some FETs does not always represent a constant power product and should be checked, if the line is not constant power then more points should be checked. For example, check VMAX at 13.2V with IFLBMIN = 16A, derated to 40A. In this case, the 6.3V SOA is very similar. If there is no specific requirement for the fault filter, it is recommended to reduce this value further to account for the impact of SOA tolerance and inaccuracy. Assume a 50% reduction, which becomes 0.4ms.

Summary of key indicators/component selection in this section:
TSOA_MAX=400μs

Power-up Analysis
Having selected the timer, it is now necessary to check whether the load capacitor has enough time to complete the power-up, which is determined by the time at which the startup current curve intersects the current limit value, i.e. the effective time of the timer during power-up.

Figure 7

During the power-up phase, the controller will usually reach the current limit due to the inrush current required by the load capacitor. If the time set by the TIMER pin is not enough for the load capacitor to charge, the MOSFET will be disabled and the system will not be able to power up. The average current limit of the foldback system can be used to estimate the power-up time. Since the time required exceeds the determined SOA limit, the system will not be able to power up the load capacitor of this size. To solve this problem, the inrush current needs to be reduced to below the hot-swap control limit during power-up. This is achieved by increasing the effective gate capacitance, which slows down the power-up time and reduces the inrush current. In this way, the inrush is controlled by an open-loop source follower system. In order to avoid exceeding the current limit (16A), the gate capacitance is selected to reduce the inrush current to about 10A.

Summary of key indicators/component selection in this section:
CGATE=15nF
TPOWERUP=7.5ms

Timer Capacitor
After determining the MOSFET SOA requirement and obtaining a satisfactory power-up time, the TIMER capacitor value can now be obtained to be approximately 22nF.

Power in MOSFET at startup
As a final step, we need to check if the power dissipated in the FET at startup is within the SOA limit of the MOSFET. The energy required to charge the load capacitor can be calculated by:
PMOSFET = TRISE / RthIA = 60 / 40 = 1.5W
If we check the SOA again, we can see that 6.3V and 22A correspond to values ​​over 10ms, meeting the SOA limit.